UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 382

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

19.1.2 Registers controlling standby function
(1) Oscillation stabilization time counter status register (OSTC)
380
The standby function is controlled by the following two registers.
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
This is the status register of the high-speed system clock oscillation stabilization time counter. If the internal
oscillation clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be
checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
Reset release (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction, MSTOP (bit 7 of
MOC register) = 1, or MCC (bit 7 of PCC register) = 1 clear OSTC to 00H.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and remain 1.
Address: FFA3H
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Symbol
OSTC
Figure 19-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
2. If the STOP mode is entered and then released while the internal oscillation clock is being
3. The wait time when STOP mode is released does not include the time after STOP mode
Remark f
MOST11
used as the CPU clock, set the oscillation stabilization time as follows.
The oscillation stabilization time counter counts only during the oscillation stabilization
time set by OSTS. Therefore, note that only the statuses during the oscillation stabilization
time set by OSTS are set to OSTC after STOP mode has been released.
release until clock oscillation starts (“a” below) regardless of whether STOP mode is
released by RESET input or interrupt generation.
7
0
1
1
1
1
1
Desired OSTC oscillation stabilization time
After reset: 00H
XP
: High-speed system clock oscillation frequency
MOST13
6
0
0
1
1
1
1
X1 pin voltage
waveform
CHAPTER 19 STANDBY FUNCTION
R
MOST14
User’s Manual U16899EJ3V0UD
5
0
0
0
1
1
1
STOP mode release
MOST11
MOST15
4
0
0
0
1
1
a
MOST13
MOST16
3
0
0
0
0
1
Oscillation stabilization time set by OSTS
2
2
2
2
2
MOST14
11
13
14
15
16
Oscillation stabilization time status
/f
/f
/f
/f
/f
XP
XP
XP
XP
XP
2
min.
min.
min.
min.
min.
f
204.8 s min. 128 s min.
819.2 s min. 512 s min.
1.64 ms min. 1.02 ms min.
3.27 ms min. 2.04 ms min.
6.55 ms min. 4.09 ms min.
XP
MOST15
= 10 MHz f
1
XP
MOST16
= 16 MHz
0