UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 129

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes 1.
2.
3.
4.
CPU clock: f
f
f
XP
R
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
When shifting from status 2 to status 1, make sure that MCS is 0.
The watchdog timer operates using internal oscillator even in STOP mode if “internal oscillator cannot
be stopped” is selected by the option byte. Internal oscillation clock division can be selected as the
count source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request
before watchdog timer overflow. If this processing is not performed, an internal reset signal is
generated at watchdog timer overflow after STOP instruction execution.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
: Oscillating
: Oscillating
Status 3
(3) When “internal oscillator cannot be stopped” is selected by option byte
XP
instruction
Interrupt
STOP
MCM0 = 1
Figure 5-13. Status Transition Diagram (3/4)
MCM0 = 0
(when subsystem clock is not used)
Interrupt
HALT
instruction
CHAPTER 5 CLOCK GENERATOR
Note 1
User’s Manual U16899EJ3V0UD
instruction
Interrupt
STOP
f
CPU clock: f
f
XP
R
STOP
: Oscillating
: Oscillating
Status 2
HALT
Note 3
HALT
instruction
Interrupt
R
Interrupt
instruction
MSTOP = 1
MSTOP = 0
STOP
Reset release
HALT instruction
Interrupt
Note 2
f
XP
: Oscillation stopped
CPU clock: f
f
Reset
R
: Oscillating
Status 1
Note 4
R
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