UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 400

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

20.1 Register for Confirming Reset Source
store which source has generated the reset request.
398
Many internal reset generation sources exist in the 78K0/KE1+. The reset control flag register (RESF) is used to
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
The status of RESF when a reset request is generated is shown in Table 20-2.
Address: FFACH
Flag
WDTRF
CLMRF
LVIRF
Symbol
RESF
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
Reset Source
WDTRF
CLMRF
LVIRF
7
0
0
1
0
1
0
1
After reset: 00H
Table 20-2. RESF Status When Reset Request Is Generated
Figure 20-5. Format of Reset Control Flag Register (RESF)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Cleared (0)
RESET Input
6
0
Note
CHAPTER 20 RESET FUNCTION
R
User’s Manual U16899EJ3V0UD
5
0
Cleared (0)
Reset by POC
Internal reset request by low-voltage detector (LVI)
Internal reset request by watchdog timer (WDT)
Internal reset request by clock monitor (CLM)
WDTRF
4
Set (1)
Held
Held
Reset by WDT
3
0
Held
Set (1)
Held
Reset by CLM
2
0
CLMRF
1
Held
Held
Set (1)
Reset by LVI
LVIRF
0