UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 470

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

468
16-bit data
transfer
8-bit
operation
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
4.
MOVW
XCHW
ADD
ADDC
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Only when rp = BC, DE or HL
Except “r = A”
control register (PCC).
rp, #word
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
sfrp, AX
AX, rp
rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
Note 3
Note 3
Note 3
Note 4
Note 4
CHAPTER 28 INSTRUCTION SET
User’s Manual U16899EJ3V0UD
Bytes
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
10
10
6
8
6
6
4
4
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
10
10
12
12
8
8
8
8
8
5
9
5
9
9
9
8
5
9
5
9
9
9
rp
(saddrp)
sfrp
AX
(saddrp)
AX
sfrp
AX
rp
AX
(addr16)
AX
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
word
AX
(saddrp)
sfrp
rp
(addr16)
rp
word
AX
r + A
r + A + CY
A + byte
A + r
A + (saddr)
A + (addr16)
A + (HL)
A + (HL + byte)
A + (HL + B)
A + (HL + C)
A + byte + CY
A + r + CY
A + (saddr) + CY
A + (addr16) + C
A + (HL) + CY
A + (HL + byte) + CY
A + (HL + B) + CY
A + (HL + C) + CY
word
AX
AX
CPU
(saddr) + byte
(saddr) + byte + CY
) selected by the processor clock
Operation
Z AC CY
Flag