UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 558

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

556
Multiplier/
divider
Interrupt
Function
SDR0:
Remainder data
register 0
MDA0H,
MDA0L:
Multiplication/
division data
register A0
MDB0:
Multiplication/
division data
register B0
DMUC:
Multiplier/divide
r control register
0
IF1H: Interrupt
request flag
register
IF0L, IF0H,
IF1L, IF1H:
Interrupt
request flag
registers
MK1H: Interrupt
mask flag
register
Details of
Function
The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
SDR0 is reset when the operation is started (when DMUE is set to 1).
MDA0H is cleared to 0 when an operation is started in the multiplication mode
(when multiplier/divider control register 0 (DMUC0) is set to 81H).
Do not change the value of MDA0 during operation processing (while bit 7 (DMUE)
of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the
operation is executed, but the result is undefined.
The value read from MDA0 during operation processing (while DMUE is 1) is not
guaranteed.
Do not change the value of MDB0 during operation processing (while bit 7 (DMUE)
of multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the
operation is executed, but the result is undefined.
Do not clear MDB0 to 0000H in the division mode. If set, undefined operation
results are stored in MDA0 and SDR0.
If DMUE is cleared to 0 during operation processing (when DMUE is 1), the
operation result is not guaranteed. If the operation is completed while the clearing
instruction is being executed, the operation result is guaranteed, provided that the
interrupt flag is set.
Do not change the value of DMUSEL0 during operation processing (while DMUE
is 1). If it is changed, undefined operation results are stored in
multiplication/division data register A0 (MDA0) and remainder data register 0
(SDR0).
If DMUE is cleared to 0 during operation processing (while DMUE is 1), the
operation processing is stopped. To execute the operation again, set
multiplication/division data register A0 (MDA0), multiplication/division data register
B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start the
operation (by clearing DMUE to 1).
Be sure to clear bits 4 to 7 of IF1H to 0.
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag
may be set by noise.
Use the 1-bit memory manipulation instruction (CLR1) for manipulating the flag of
the interrupt request flag register. A 1-bit manipulation instruction such as “IF0L.0
= 0;” and “_asm(“clr1 IF0L, 0”);” should be used when describing in C language,
because assembly instructions after compilation must be 1-bit memory
manipulation instructions (CLR1).
If an 8-bit memory manipulation instruction “IF0L & = 0xfe;” is described in C
language, for example, it is converted to the following three assembly instructions
after compilation:
mov
and
mov
In this case, at the timing after “mov a, IF0L” to “mov IF0L, a”, if the request flag of
another bit of the identical interrupt request flag register (IF0L) is set to 1, it is
cleared to 0 by “mov IF0L, a”. Therefore, care must be exercised when using the
8-bit memory manipulation instruction in C language.
Be sure to set bits 4, 6, and 7 of MK1H to 1. Be sure to clear bit 5 of MK1H to 0.
a, IF0L
a, #0FEH
IF0L, a
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
Cautions
p. 350
p. 350
p. 350
p. 350
p. 350
p. 351
p. 351
p. 352
p. 352
p. 352
p. 363
p. 363
p. 364
p. 365
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