C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet

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C8051F320

Manufacturer Part Number
C8051F320
Description
IC 8051 MCU 16K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F32xr
Datasheet

Specifications of C8051F320

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Preliminary Rev. 1.1 12/03
ANALOG PERIPHERALS
-
-
-
-
USB FUNCTION CONTROLLER
-
-
-
-
-
-
ON-CHIP DEBUG
-
-
-
VOLTAGE REGULATOR INPUT: 4.0V TO 5.25V
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
10-Bit ADC
Two Comparators
Internal Voltage Reference
POR/Brown-Out Detector
USB Specification 2.0 Compliant
Full Speed (12 Mbps) or Low Speed (1.5 Mbps)
Operation
Integrated Clock Recovery; No External Crystal
Required for Full Speed or Low Speed
Supports Eight Flexible Endpoints
1k Byte USB Buffer Memory
Integrated Transceiver; No External Resistors Required
On-Chip Debug Circuitry Facilitates Full Speed,
Non-Intrusive In-System Debug (No Emulator
Required!)
Provides Breakpoints, Single Stepping,
Inspect/Modify Memory and Registers
Superior Performance to Emulation Systems Using
ICE-Chips, Target Pods, and Sockets
Up to 200 ksps
Up to 17 or 13 External Single-Ended or Differential
Inputs
VREF from External Pin, Internal Reference, or VDD
Built-in Temperature Sensor
External Conversion Start Input
SENSOR
M
A
U
X
INTERRUPTS
PRECISION INTERNAL
TEMP
ISP FLASH
PERIPHERALS
Copyright © 2003 by Silicon Laboratories
16KB
OSCILLATOR
200ksps
HIGH-SPEED CONTROLLER CORE
16
ANALOG
10-bit
ADC
VREF
+
-
VREG
CIRCUITRY
+
-
8051 CPU
(25MIPS)
DEBUG
Full Speed USB, 16k ISP FLASH MCU Family
HIGH SPEED 8051 µC Core
-
-
-
MEMORY
-
-
DIGITAL PERIPHERALS
-
-
-
-
-
CLOCK SOURCES
-
-
-
PACKAGES
-
-
TEMPERATURE RANGE: -40°C TO +85°C
Timer 0
Timer 1
Timer 2
Timer 3
SMBus
UART
Pipelined Instruction Architecture; Executes 70% of
Instructions in 1 or 2 System Clocks
Up to 25 MIPS Throughput with 25 MHz Clock
Expanded Interrupt Handler
2304 Bytes Internal RAM (1k + 256 + 1k USB FIFO)
16k Bytes FLASH; In-system programmable in 512-byte
Sectors
25/21 Port I/O; All 5 V tolerant with High Sink Current
Hardware Enhanced SPI™, Enhanced UART, and
SMBus™ Serial Ports
Four General Purpose 16-Bit Counter/Timers
16-Bit Programmable Counter Array (PCA) with Five
Capture/Compare Modules
Real Time Clock Mode using External Clock Source and
PCA or Timer
Internal Oscillator: 0.25% Accuracy with Clock
Recovery enabled. Supports all USB and UART Modes
External Oscillator: Crystal, RC, C, or Clock (1 or 2 Pin
Modes)
Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Strategies
32-pin LQFP (C8051F320)
28-pin MLP (C8051F321)
PCA
USB Controller /
SPI
DIGITAL I/O
Transceiver
POR
2304 B
SRAM
Port 0
Port 1
Port 2
Port 3
WDT
C8051F320/1
C8051F320/1-DS11

Related parts for C8051F320

C8051F320 Summary of contents

Page 1

... Recovery enabled. Supports all USB and UART Modes - External Oscillator: Crystal, RC Clock ( Pin Modes) - Can Switch Between Clock Sources on-the-fly; Useful in Power Saving Strategies PACKAGES - 32-pin LQFP (C8051F320) - 28-pin MLP (C8051F321) TEMPERATURE RANGE: -40°C TO +85°C ANALOG DIGITAL I/O PERIPHERALS UART SPI ...

Page 2

... C8051F320/1 2 Notes Rev. 1.1 ...

Page 3

... CIP-51 MICROCONTROLLER .........................................................................................73 9.1. Instruction Set..................................................................................................................75 9.1.1. Instruction and CPU Timing..................................................................................75 9.1.2. MOVX Instruction and Program Memory.............................................................75 9.2. Memory Organization .....................................................................................................79 9.2.1. Program Memory ...................................................................................................79 9.2.2. Data Memory .........................................................................................................80 9.2.3. General Purpose Registers .....................................................................................80 9.2.4. Bit Addressable Locations .....................................................................................80 9.2.5. Stack ...................................................................................................................80 9.2.6. Special Function Registers.....................................................................................81 C8051F320/1 Rev. 1.1 3 ...

Page 4

... Accessing User XRAM .................................................................................................113 12.2.Accessing USB FIFO Space..........................................................................................114 13. OSCILLATORS...................................................................................................................117 13.1. Programmable Internal Oscillator .................................................................................117 13.1.1. Programming the Internal Oscillator on C8051F320/1 Devices .........................118 13.1.2. Internal Oscillator Suspend Mode .......................................................................118 13.2.External Oscillator Drive Circuit...................................................................................120 13.2.1. Clocking Timers Directly Through the External Oscillator ................................120 13 ...

Page 5

... SMB0CN Control Register ..................................................................................183 16.4.3. Data Register........................................................................................................186 16.5. SMBus Transfer Modes.................................................................................................187 16.5.1. Master Transmitter Mode ....................................................................................187 16.5.2. Master Receiver Mode.........................................................................................188 16.5.3. Slave Receiver Mode ...........................................................................................189 16.5.4. Slave Transmitter Mode.......................................................................................190 16.6. SMBus Status Decoding................................................................................................191 17. UART0 ..................................................................................................................................193 C8051F320/1 Rev. 1.1 5 ...

Page 6

... C8051F320/1 17.1. Enhanced Baud Rate Generation...................................................................................194 17.2.Operational Modes ........................................................................................................195 17.2.1. 8-Bit UART .........................................................................................................195 17.2.2. 9-Bit UART .........................................................................................................196 17.3.Multiprocessor Communications...................................................................................197 18. ENHANCED SERIAL PERIPHERAL INTERFACE (SPI0) .........................................203 18.1. Signal Descriptions........................................................................................................204 18.1.1. Master Out, Slave In (MOSI) ..............................................................................204 18.1.2. Master In, Slave Out (MISO) ..............................................................................204 18 ...

Page 7

... Pin Sharing...............................................................................................................255 C8051F320/1 Rev. 1.1 7 ...

Page 8

... C8051F320/1 8 Notes Rev. 1.1 ...

Page 9

... GLOBAL DC ELECTRICAL CHARACTERISTICS .....................................................30 Table 3.1. Global DC Electrical Characteristics...................................................................30 4. PINOUT AND PACKAGE DEFINITIONS .......................................................................31 Table 4.1. Pin Definitions for the C8051F320/1 ..................................................................31 Figure 4.1. LQFP-32 Pinout Diagram (Top View)................................................................33 Figure 4.2. LQFP-32 Package Diagram.................................................................................34 Table 4.2. LQFP-32 Package Dimensions............................................................................34 Figure 4.3. MLP-28 Pinout Diagram (Top View) .................................................................35 Figure 4 ...

Page 10

... C8051F320/1 Figure 5.15. ADC Window Compare Example: Right-Justified Single-Ended Data..............52 Figure 5.16. ADC Window Compare Example: Left-Justified Single-Ended Data ................52 Figure 5.17. ADC Window Compare Example: Right-Justified Differential Data.................53 Figure 5.18. ADC Window Compare Example: Left-Justified Differential Data ...................53 Table 5.1. ADC0 Electrical Characteristics..........................................................................54 6 ...

Page 11

... Figure 14.10. P0SKIP: Port0 Skip Register...........................................................................136 Figure 14.11. P1: Port1 Register............................................................................................137 Figure 14.12. P1MDIN: Port1 Input Mode Register .............................................................137 Figure 14.13. P1MDOUT: Port1 Output Mode Register.......................................................138 Figure 14.14. P1SKIP: Port1 Skip Register...........................................................................138 Figure 14.15. P2: Port2 Register............................................................................................139 C8051F320/1 Rev. 1.1 11 ...

Page 12

... C8051F320/1 Figure 14.16. P2MDIN: Port2 Input Mode Register .............................................................139 Figure 14.17. P2MDOUT: Port2 Output Mode Register.......................................................140 Figure 14.18. P2SKIP: Port2 Skip Register...........................................................................140 Figure 14.19. P3: Port3 Register............................................................................................141 Figure 14.20. P3MDIN: Port3 Input Mode Register .............................................................141 Figure 14.21. P3MDOUT: Port3 Output Mode Register.......................................................142 Table 14 ...

Page 13

... Figure 18.13. SPI Master Timing (CKPHA = 1)...................................................................214 Figure 18.14. SPI Slave Timing (CKPHA = 0) .....................................................................215 Figure 18.15. SPI Slave Timing (CKPHA = 1) .....................................................................215 Table 18.1. SPI Slave Timing Parameters............................................................................216 19. TIMERS ..............................................................................................................................217 Figure 19.1. T0 Mode 0 Block Diagram................................................................................218 Figure 19.2. T0 Mode 2 Block Diagram................................................................................219 C8051F320/1 Rev. 1.1 13 ...

Page 14

... C8051F320/1 Figure 19.3. T0 Mode 3 Block Diagram................................................................................220 Figure 19.4. TCON: Timer Control Register.........................................................................221 Figure 19.5. TMOD: Timer Mode Register...........................................................................222 Figure 19.6. CKCON: Clock Control Register......................................................................223 Figure 19.7. TL0: Timer 0 Low Byte ....................................................................................224 Figure 19.8. TL1: Timer 1 Low Byte ....................................................................................224 Figure 19 ...

Page 15

... Figure 21.1. C2ADD: C2 Address Register ..........................................................................253 Figure 21.2. DEVICEID: C2 Device ID Register .................................................................253 Figure 21.3. REVID: C2 Revision ID Register .....................................................................254 Figure 21.4. FPCTL: C2 FLASH Programming Control Register ........................................254 Figure 21.5. FPDAT: C2 FLASH Programming Data Register ............................................254 Figure 21.6. Typical C2 Pin Sharing .....................................................................................255 C8051F320/1 Rev. 1.1 15 ...

Page 16

... C8051F320/1 16 Notes Rev. 1.1 ...

Page 17

... Each device is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-40°C to +85°C). (Note that 3.0 V-to-3 required for USB communication.) The Port I/O and /RST pins are tolerant of input signals C8051F320/1 are available in a 32-pin LQFP or a 28-pin MLP package. Table 1.1. Product Selection Guide ...

Page 18

... C8051F320/1 Figure 1.1. C8051F320 Block Diagram 5.0V Voltage Enable REGIN IN Regulator OUT Analog/Digital VDD Power GND C2D Debug HW /RST/C2CK Brown- POR Out XTAL1 XTAL2 External Oscillator Circuit 12MHz Internal x4 2 Oscillator 2 USB Clock Clock 1,2,3,4 Recovery USB D+ Transceiver D- VBUS 18 Port 0 Latch ...

Page 19

... Reset SRAM SMBus 1 1K byte SPI XRAM C Port 2 o Latch r SFR Bus System e Clock Port 3 Latch VREF VREF USB VDD Controller 10-bit 200ksps ADC SRAM Rev. 1.1 C8051F320/1 P0.0 P P0.1 0 P0.2/XTAL1 P0.3/XTAL2 P0.4 D P0.5 r P0.6/CNVSTR v P0.7/VREF P1.2 P1 P1.5 ...

Page 20

... CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F320/1 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compat- ible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The CIP-51 core offers all the peripherals included with a standard 8052, including four 16-bit counter/timers, a full-duplex UART with extended baud rate configuration, an enhanced SPI port, 2304 bytes of on-chip RAM, 128 byte Special Function Register (SFR) address space, and 25/21 I/O pins ...

Page 21

... Additional Features The C8051F320/1 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve per- formance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...

Page 22

... C8051F320/1 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indi- rect addressing ...

Page 23

... Transceiver VDD D+ D- 1.4. Voltage Regulator C8051F320/1 devices include a 5 V-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software. Serial Interface Engine (SIE) Endpoint0 IN/OUT USB Data ...

Page 24

... The C8051F310DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F320/1 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and an RS-232 to C2 serial adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the RS-232 and C2 cables, and wall-mount power sup- ply ...

Page 25

... C8051F320 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port); C8051F321 devices include 21 I/O pins (two byte-wide Ports, one 4-bit-wide Port, and one 1-bit-wide Port). The C8051F320/1 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. ...

Page 26

... C8051F320/1 1.8. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with five programmable capture/com- pare modules. The PCA clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflows, an External Clock Input (ECI), the system clock, or the external oscillator clock source divided by 8 ...

Page 27

... Analog to Digital Converter The C8051F320/1 devices include an on-chip 10-bit SAR ADC with a 17-channel differential input multiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs. Ports1-3 are available as ADC inputs ...

Page 28

... C8051F320/1 1.10. Comparators C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time is programmable, allowing the user to select between high-speed and low-power modes ...

Page 29

... Note: stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indi- cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F320/1 * CONDITIONS MIN ...

Page 30

... C8051F320/1 3. GLOBAL DC ELECTRICAL CHARACTERISTICS Table 3.1. Global DC Electrical Characteristics -40°C to +85°C, 25 MHz System Clock unless otherwise specified. PARAMETER Digital Supply Voltage (Note 1) Digital Supply Current with CPU VDD=3.3V, Clock=24MHz active VDD=3.3V, Clock=1MHz VDD=3.3V, Clock=32kHz Digital Supply Current with CPU VDD=3.3V, Clock=24MHz active and USB active (Full or Low VDD=3 ...

Page 31

... PINOUT AND PACKAGE DEFINITIONS Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name ‘F320 ‘F321 VDD 6 6 GND 3 3 /RST C2CK P3. C2D REGIN 7 7 VBUS P0 P0 P0. XTAL1 P0. XTAL2 P0 P0 Type Description Power In 2.7-3.6 V Power Supply Voltage Input. Power Out 3.3 V Voltage Regulator Output. See Ground ...

Page 32

... C8051F320/1 Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name ‘F320 ‘F321 P0. CNVSTR P0. VREF P2.4 14 P2 Type Description Port 0.6. See Section 14 for a complete description. ADC0 External Convert Start Input. See D I/O Port 0.7. See Section 14 for a complete description ...

Page 33

... Table 4.1. Pin Definitions for the C8051F320/1 Pin Numbers Name Type ‘F320 ‘F321 D I Figure 4.1. LQFP-32 Pinout Diagram (Top View) 1 P0.1 2 P0.0 3 GND VDD 7 REGIN 8 VBUS Description Port 2.7. See Section 14 for a complete description. C8051F320 Top View Rev. 1.1 ...

Page 34

... C8051F320/1 Figure 4.2. LQFP-32 Package Diagram PIN 1 IDENTIFIER Table 4.2. LQFP-32 Package Dimensions MIN 0.05 A2 1. Rev. 1.1 MM TYP MAX - 1.60 - 0.15 1.40 1.45 0.37 0.45 9.00 - 7.00 - 0.80 - 9.00 - 7.00 - ...

Page 35

... Figure 4.3. MLP-28 Pinout Diagram (Top View) GND P0.1 1 P0.0 2 GND 3 C8051F321 D+ 4 Top View D- 5 VDD 6 REGIN 7 C8051F320 GND 15 Rev. 1.1 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 35 ...

Page 36

... C8051F320/1 Figure 4.4. MLP-28 Package Drawing Bottom View DETAIL Side View DETAIL Rev. 1.1 Table 4.2. MLP-28 Package Dimensions MM MIN TYP MAX A 0.80 0.90 1. 0.02 0. 0. 0.18 0. 2.90 3. 2.90 3. 0.45 0. 0.435 - BB - 0.435 ...

Page 37

... Figure 4.5. Typical MLP-28 Landing Diagram 0.50 mm 0.20 mm Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm C8051F320/1 Top View E2 E Rev. 1.1 0. ...

Page 38

... C8051F320/1 Figure 4.6. Typical MLP-28 Solder Mask 0.50 mm 0.60 mm 0. 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0. Top View 0.60 mm 0.30 mm 0. Rev. 1.1 0.85 mm ...

Page 39

... ADC (ADC0) The ADC0 subsystem for the C8051F320/1 consists of two analog multiplexers (referred to collectively as AMUX0) with 17 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track- and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configurable under software control via the Special Function Registers shown in Figure 5 ...

Page 40

... C8051F320/1 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.0, the on-chip temperature sensor, or the positive power supply (VDD). Any of the following may be selected as the negative input: P1.0-P3.0, VREF, or GND. When GND is selected as the negative input, ADC0 operates in Single-ended Mode ...

Page 41

... ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. Figure 5.2. Typical Temperature Sensor Transfer Function (mV) 1000 900 800 700 600 500 -50 Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. C8051F320 2.86(TEMP ) + 776 mV TEMP 100 (Celsius) Rev. 1 the positive ...

Page 42

... C8051F320/1 5.3. Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + 1) for 0 ≤ AD0SC ≤ 31). 5.3.1. Starting a Conversion A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start of Conver- sion Mode bits (AD0CM2-0) in register ADC0CN ...

Page 43

... SAR Clocks Low Power AD0TM=1 or Convert SAR Clocks Track or AD0TM=0 Convert 44 Track Convert Track or Convert Convert B. ADC0 Timing for Internal Trigger Source Track Convert Convert Rev. 1.1 C8051F320 Low Power Mode Track Low Power Mode 10 11 Track 43 ...

Page 44

... C8051F320/1 5.3.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conver- sion ...

Page 45

... C8051F320; selection RESERVED on C8051F321 devices. R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ADC0 Positive Input P1.0 P1.1 P1 ...

Page 46

... C8051F320; selection RESERVED on C8051F321 devices. 46 R/W R/W R/W AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit4 Bit3 Bit2 ADC0 Negative Input P1.0 P1.1 P1 ...

Page 47

... For AD0LJST = 1: Bits 7-0 are the most-significant bits of the 10-bit ADC0 Data Word. R/W R/W R/W AD0SC1 AD0SC0 AD0LJST Bit4 Bit3 Bit2 R/W R/W R/W Bit4 Bit3 Bit2 Rev. 1.1 C8051F320/1 R/W R/W Reset Value - - 11111000 Bit1 Bit0 SFR Address: 0xBC R/W R/W Reset Value 00000000 Bit1 Bit0 ...

Page 48

... C8051F320/1 Figure 5.9. ADC0L: ADC0 Data Word LSB Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word Low-Order Bits. For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the 10-bit Data Word. For AD0LJST = 1: Bits 7-6 are the lower 2 bits of the 10-bit Data Word. Bits 5-0 will always read ‘0’. ...

Page 49

... ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved. R/W R/W R/W R/W AD0CM1 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value AD0CM0 00000000 Bit0 SFR Address: 0xE8 (bit addressable) 49 ...

Page 50

... C8051F320/1 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times. The window detector interrupt flag (AD0WINT in register ADC0CN) can also be used in polled mode ...

Page 51

... Bits7-0: Low byte of ADC0 Less-Than Data Word. R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value 00000000 Bit0 SFR Address: 0xC6 R/W Reset Value 00000000 Bit0 SFR Address: 0xC5 51 ...

Page 52

... C8051F320/1 5.4.1. Window Detector In Single-Ended Mode Figure 5.15 shows two example ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF * (1023/1024) with respect to GND, and is represented by a 10-bit unsigned inte- ger value. In the left example, an AD0WINT interrupt will be generated if the ADC0 conversion word (ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL (if 0x0040 < ...

Page 53

... ADC0H:ADC0L Input Voltage (Px.x - Px.y) VREF x (511/512) 0x7FC0 0x1040 VREF x (64/512) 0x1000 0x0FC0 AD0WINT=1 0x0000 VREF x (-1/512) 0xFFC0 0xFF80 0x8000 -VREF Rev. 1.1 C8051F320/1 differential data, with AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT=1 AD0WINT=1 ADC0GTH:ADC0GTL AD0WINT not affected ADC0LTH:ADC0LTL AD0WINT=1 53 ...

Page 54

... C8051F320/1 Table 5.1. ADC0 Electrical Characteristics VDD = 3.0 V, VREF = 2.40 V, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient DYNAMIC PERFORMANCE (10 kHz sine-wave Single-ended input below Full Scale, 200 ksps) ...

Page 55

... VOLTAGE REFERENCE The Voltage reference MUX on C8051F320/1 devices is configurable to use an externally connected voltage refer- ence, the internal reference voltage generator, or the power supply voltage VDD (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal reference or an external source, REFSL should be set to ‘ ...

Page 56

... C8051F320/1 Figure 6.2. REF0CN: Reference Control Register R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. 1: VDD used as voltage reference. ...

Page 57

... COMPARATORS C8051F320/1 devices include two on-chip programmable voltage Comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two Comparators operate identically with the following exceptions: (1) Their input selections differ as shown in Figure 7.1 and Figure 7.2; (2) Comparator0 can be used as a reset source. ...

Page 58

... CP1RIF CP1FIF CP1HYP1 CMX1N1 CP1HYP0 CMX1N0 CP1HYN1 CP1HYN0 CMX1P1 CMX1P0 P1.2 P1.6 P2.2 P2.6 P1.3 P1.7 P2.3 P2.7 Note: P2.6 and P2.7 available only on C8051F320 58 for details on configuring Comparator outputs VDD CP1 + + SET SET CLR CLR (SYNCHRONIZER) GND CP1 - CP1RIE CP1FIE ...

Page 59

... The Comparator is enabled by setting the CPnEN bit to ‘1’, and is disabled by clearing this bit to ‘0’. OUT Negative Hysteresis Voltage (Programmed by CP0HYN Bits) Negative Hysteresis Maximum Disabled Negative Hysteresis Maximum Positive Hysteresis 58.) The CPnFIF flag is set to ‘1’ upon a Com- Rev. 1.1 C8051F320/1 59 ...

Page 60

... C8051F320/1 Figure 7.4. CPT0CN: Comparator0 Control Register R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage on CP0+ > CP0-. Bit5: CP0RIF: Comparator0 Rising-Edge Flag. ...

Page 61

... CMX0P1-CMX0P0: Comparator0 Positive Input MUX Select. These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P0 Positive Input † Note: P2.4 and P2.5 available only on C8051F320 devices; selection reserved on C8051F321 devices. R/W R/W R/W R CMX0P1 Bit4 Bit3 Bit2 Bit1 P1 ...

Page 62

... C8051F320/1 Figure 7.6. CPT0MD: Comparator0 Mode Selection Register R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. ...

Page 63

... CP1HYN1-0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. R/W R/W R/W CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit4 Bit3 Bit2 Rev. 1.1 C8051F320/1 R/W R/W Reset Value Bit1 Bit0 SFR Address: 0x9A 63 ...

Page 64

... CMX1P1-CMX1P0: Comparator1 Positive Input MUX Select. These bits select which Port pin is used as the Comparator1 positive input. CMX1P1 CMX1P0 † Note: P2.6 and P2.7 available only on C8051F320 devices; selection reserved on C8051F321 devices. 64 R/W R/W R Bit4 Bit3 Bit2 Negative Input P1.3 P1.7 P2.3 † ...

Page 65

... These bits select the response time for Comparator1. Mode CP1MD1 CP1MD0 CP1 Response Time (TYP R/W R/W R/W CP1FIE - - CP1MD1 Bit4 Bit3 Bit2 0 100 ns 1 175 ns 0 320 ns 1 1050 ns Rev. 1.1 C8051F320/1 R/W R/W Reset Value CP1MD0 00000010 Bit1 Bit0 SFR Address: 0x9C 65 ...

Page 66

... C8051F320/1 Table 7.1. Comparator Electrical Characteristics VDD = 3.0 V, -40°C to +85°C unless otherwise noted. All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. PARAMETER CP0+ - CP0- = 100 mV Response Time: † Mode 0, Vcm = 1.5 V CP0+ - CP0- = -100 mV CP0+ - CP0- = 100 mV Response Time: † ...

Page 67

... VOLTAGE REGULATOR (REG0) C8051F320/1 devices include a 5 V-to-3 V voltage regulator (REG0). When enabled, the REG0 output appears on the VDD pin and can be used to power external devices. REG0 can be enabled/disabled by software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. ...

Page 68

... C8051F320/1 8.1. Regulator Mode Selection REG0 offers a low power mode intended for use when the device is in suspend mode. In this low power mode, the REG0 output remains as specified; however the REG0 dynamic performance (response time) is degraded. See Table 8.1 for normal and low power mode supply current specifications. The REG0 mode selection is controlled via the REGMOD bit in register REG0CN ...

Page 69

... Section “15. Universal Serial Bus Controller (USB0)” on Section “10. Reset Sources” on page 99 CONDITIONS Output Current = 1 to 100 mA Normal Mode (REGMOD = ‘0’) Low Power Mode (REGMOD = ‘1’) Rev. 1.1 C8051F320/1 for details on selecting MIN TYP MAX UNITS 4.0 5. ...

Page 70

... Figure 8.2. REG0 Configuration: USB Self-Powered From VBUS From 5V REGIN Power Net To 3V Power Net 70 C8051F320/1 VBUS Sense 5V In Voltage Regulator (REG0) VDD C8051F320/1 VBUS VBUS Sense 5V In Voltage Regulator (REG0) VDD Rev. 1.1 3V Out Device Power Net 3V Out Device Power Net ...

Page 71

... From 3V VDD Power Net Figure 8.4. REG0 Configuration: No USB Connection C8051F320/1 VBUS From 5V REGIN Power Net To 3V VDD Power Net C8051F320/1 VBUS Sense 5V In Voltage Regulator (REG0) 3V Out Power Net VBUS Sense 5V In Voltage Regulator (REG0) 3V Out Power Net Rev. 1.1 ...

Page 72

... C8051F320/1 Figure 8.5. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network). 1: VBUS signal currently preset (device attached to USB network). ...

Page 73

... REGISTER DATA BUS BUFFER D8 SFR BUS D8 D8 INTERFACE D8 MEMORY A16 INTERFACE PIPELINE D8 INTERRUPT INTERFACE D8 D8 REGISTER Rev. 1.1 C8051F320/1 17), an Enhanced SPI (see description (Section 9.2.6), STACK POINTER SRAM (256 X 8) SFR_ADDRESS SFR_CONTROL SFR_WRITE_DATA SFR_READ_DATA MEM_ADDRESS MEM_CONTROL MEM_WRITE_DATA MEM_READ_DATA SYSTEM_IRQs EMULATION_IRQ 73 ...

Page 74

... C8051F320/1 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to exe- cute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instruc- tions in one or two system clock cycles, with no instructions taking more than eight system clock cycles ...

Page 75

... MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory (Note: the C8051F320/1 does not support off-chip data or program memory). In the CIP-51, the MOVX write instruction is used to accesses external RAM (XRAM) and the on-chip program memory space implemented as re-programmable FLASH memory ...

Page 76

... C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND Register to A ANL A, direct AND direct byte to A ANL A, @Ri AND indirect RAM to A ANL A, #data AND immediate to A ANL direct, A AND A to direct byte ...

Page 77

... CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to A and jump if not equal CJNE Rn, #data, rel Compare immediate to Register and jump if not equal BOOLEAN MANIPULATION PROGRAM BRANCHING Rev. 1.1 C8051F320/1 Clock Bytes Cycles ...

Page 78

... C8051F320/1 Table 9.1. CIP-51 Instruction Set Summary Mnemonic Description CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank ...

Page 79

... Byte Sectors) 0x0000 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F320/1 implements 16k bytes of this program memory space as in-system, re-programmable FLASH memory, organized in a contiguous block from addresses 0x0000 to 0x3FFF. Addresses above 0x3DFF are reserved. Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory by setting the Program Store Write Enable bit (PSCTL ...

Page 80

... C8051F320/1 9.2.2. Data Memory The CIP-51 includes 256 of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers ...

Page 81

... AMX0P ADC0CF ADC0L OSCICL SPI0DAT P0MDOUT P1MDOUT P2MDOUT CPT0CN CPT1MD CPT0MD TMR3L TMR3H TL1 TH0 TH1 DPH 3(B) 4(C) 5(D) Rev. 1.1 C8051F320/1 VDM0CN EIP1 EIP2 RSTSRC EIE1 EIE2 P2SKIP USB0XCN ADC0LTH ADC0H FLSCL FLKEY P3MDOUT CPT1MX CPT0MX USB0ADR USB0DAT CKCON ...

Page 82

... C8051F320/1 Table 9.3. Special Function Registers Register Address Description ADC0LTL 0xC5 ADC0 Less-Than Compare Word Low AMX0N 0xBA AMUX0 Negative Channel Select AMX0P 0xBB AMUX0 Positive Channel Select B 0xF0 B Register CKCON 0x8E Clock Control CLKSEL 0xA9 Clock Select CPT0CN 0x9B Comparator0 Control ...

Page 83

... Timer/Counter 2 Reload Low TMR3CN 0x91 Timer/Counter 3Control TMR3H 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low TMR3RLH 0x93 Timer/Counter 3 Reload High TMR3RLL 0x92 Timer/Counter 3 Reload Low C8051F320/1 Rev. 1.1 Page No. 252 252 252 252 252 252 252 250 250 250 250 250 251 ...

Page 84

... C8051F320/1 Table 9.3. Special Function Registers Register Address Description VDM0CN 0xFF VDD Monitor Control XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 0x84-0x86, 0xAB-0xAF, 0xB4, 0xB5, 0xBF, 0xC7, 0xCE, Reserved 0xCF, 0xD2, 0xD3, 0xDF, 0xE3, 0xE5, 0xF5 9 ...

Page 85

... R/W R/W R/W R/W RS1 RS0 OV F1 Bit4 Bit3 Bit2 Bit1 Address 0 0x00 - 0x07 1 0x08 - 0x0F 2 0x10 - 0x17 3 0x18 - 0x1F Rev. 1.1 C8051F320/1 R/W Reset Value 00000111 Bit0 SFR Address: 0x81 R Reset Value PARITY 00000000 Bit0 SFR Address: 0xD0 (bit addressable) 85 ...

Page 86

... C8051F320/1 R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second accumulator for certain arithmetic operations. ...

Page 87

... MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in Table 9.4 on page 89. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its inter- rupt-pending flag(s). C8051F320/1 Rev. 1.1 87 ...

Page 88

... C8051F320/1 9.3.2. External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensitive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active low; the IT0 and IT1 bits in TCON (Section “ ...

Page 89

... CCFn (PCA0CN.n) CP0FIF (CPT0CN. CP0RIF (CPT0CN.5) CP1FIF (CPT1CN. CP1RIF (CPT1CN.5) TF3H (TMR3CN. TF3L (TMR3CN.6) 15 N/A N/A N/A Rev. 1.1 C8051F320/1 Enable Priority Flag Control Always Always Enabled Highest Y EX0 (IE.0) PX0 (IP.0) Y ET0 (IE.1) PT0 (IP.1) Y EX1 (IE.2) PX1 (IP.2) Y ET1 (IE.3) PT1 (IP ...

Page 90

... C8051F320/1 9.3.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). ...

Page 91

... This bit sets the priority of the External Interrupt 0 interrupt. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. R/W R/W R/W R/W PS0 PT1 PX1 PT0 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value PX0 10000000 Bit0 SFR Address: 0xB8 (bit addressable) 91 ...

Page 92

... C8051F320/1 Figure 9.11. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3L or TF3H flags. Bit6: ECP1: Enable Comparator1 (CP1) Interrupt ...

Page 93

... This bit sets the priority of the SMB0 interrupt. 0: SMB0 interrupt set to low priority level. 1: SMB0 interrupt set to high priority level. R/W R/W R/W PPCA0 PADC0 PWADC0 PUSB0 Bit4 Bit3 Bit2 Rev. 1.1 C8051F320/1 R/W R/W Reset Value PSMB0 00000000 Bit1 Bit0 SFR Address: 0xF6 93 ...

Page 94

... C8051F320/1 Figure 9.13. EIE2: Extended Interrupt Enable 2 R/W R/W R Bit7 Bit6 Bit5 Bits7-1: UNUSED. Read = 0000000b. Write = don’t care. Bit0: EVBUS: Enable VBUS Level Interrupt. This bit sets the masking of the VBUS interrupt. 0: Disable all VBUS interrupts. 1: Enable interrupt requests generated by VBUS level sense. ...

Page 95

... R/W R/W R/W IN1SL0 IN0PL IN0SL2 IN0SL1 Bit4 Bit3 Bit2 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 Rev. 1.1 C8051F320/1 R/W R/W Reset Value IN0SL0 00000001 Bit1 Bit0 SFR Address: 0xE4 95 ...

Page 96

... C8051F320/1 9.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all interrupts, are inactive, and the internal oscillator is stopped (analog peripherals remain in their selected states ...

Page 97

... CPU goes into Idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) R/W R/W R/W R/W GF2 GF1 GF0 STOP Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value IDLE 00000000 Bit0 SFR Address: 0x87 97 ...

Page 98

... C8051F320/1 98 Notes Rev. 1.1 ...

Page 99

... Figure 10.1. Reset Sources VDD Supply Monitor Enable + - Power On Reset + - C0RSEF Missing Clock Detector (one- PCA shot) Software Reset (SWRSF) WDT EN Errant FLASH EN Operation CIP-51 Microcontroller System Reset Core Extended Interrupt Handler Rev. 1.1 C8051F320/1 (Section '0' /RST (wired-OR) Reset Funnel USB VBUS Controller Transition 99 ...

Page 100

... C8051F320/1 10.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above V Power-On Reset delay (T ) occurs before the device is released from reset; this delay is typically less than PORDelay 0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing. ...

Page 101

... VDD is above the VDD monitor threshold. Bits5-0: Reserved. Read = Variable. Write = don’t care Reserved Reserved Reserved Reserved Bit4 Bit3 Bit2 Rev. 1.1 C8051F320/1 , the power supply monitor will RST R R Reset Value Reserved Variable Bit1 Bit0 SFR Address: 0xFF 101 ...

Page 102

... C8051F320/1 10.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the /RST pin may be necessary to avoid erroneous noise-induced resets. See Table 10.1 for complete /RST pin specifications. The PINRSF flag (RSTSRC ...

Page 103

... The voltage on the VBUS pin matches the polarity selected by the VBPOL bit in register REG0CN. See Section “8. Voltage Regulator (REG0)” on page 67 The USBRSF bit will read ‘1’ following a USB reset. The state of the /RST pin is unaffected by this reset. C8051F320/1 Section “15. Universal Serial Bus Controller for details on the VBUS detection circuit. ...

Page 104

... C8051F320/1 Figure 10.4. RSTSRC: Reset Source Register R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. ...

Page 105

... Minimum /RST Low Time to Generate a System Reset VDD Monitor Turn-on Time VDD Monitor Supply Current CONDITIONS MIN = 8.5 mA, VDD = 2 3.6 V 0.7 x VDD 2.40 100 100 Rev. 1.1 C8051F320/1 TYP MAX UNITS 0 0.3 x VDD 25 40 µA 2.55 2.70 V ...

Page 106

... C8051F320/1 106 Notes Rev. 1.1 ...

Page 107

... Step 5. Set the PSWE bit (register PSCTL). Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE bit (register PSCTL). Step 8. Clear the PSEE bit (register PSCTI). C8051F320/1 Section “21. C2 Interface” on page Rev. 1.1 253. 107 ...

Page 108

... CONDITIONS FLASH Size Endurance Erase Cycle Time 25 MHz System Clock Write Cycle Time 25 MHz System Clock † Note: 512 bytes at location 0x3E00 to 0x3FFF are reserved. 108 MIN † C8051F320/1 16384 20k 10 40 Rev. 1.1 Section 11.1.2. TYP MAX UNITS bytes 100k ...

Page 109

... Lock Byte. 6. Locked pages can only be unlocked through the C2 interface with a C2 Device Erase command user firmware FLASH access attempt is denied (per restrictions #3, #4, and #5 above), a FLASH Error system reset will be generated. C8051F320/1 Rev. 1.1 109 ...

Page 110

... Setting this bit allows writing a byte of data to the FLASH program memory using the MOVX write instruction. The FLASH location should be erased before writing data. 0: Writes to FLASH program memory disabled. 1: Writes to FLASH program memory enabled; the MOVX write instruction targets FLASH memory. 110 C8051F320/1 Reserved 0x3E00 Lock Byte 0x3DFF ...

Page 111

... RESERVED. Read = 0. Must Write 0. R/W R/W R/W Bit4 Bit3 Bit2 R/W R/W R/W Reserved Reserved Reserved Reserved Bit4 Bit3 Bit2 Rev. 1.1 C8051F320/1 R/W R/W Reset Value 00000000 Bit1 Bit0 SFR Address: 0xB7 R/W R/W Reset Value Reserved 10000000 Bit1 Bit0 SFR Address: 0xB6 ...

Page 112

... C8051F320/1 112 Notes Rev. 1.1 ...

Page 113

... EXTERNAL RAM The C8051F320/1 devices include 2048 bytes of on-chip XRAM. This XRAM space is split into user RAM (addresses 0x0000 - 0x03FF) and USB0 FIFO space (addresses 0x0400 - 0x07FF). Figure 12.1. External Ram Memory Map 0xFFFF Same 2048 bytes as from 0x0000 to 0x07FF, wrapped ...

Page 114

... C8051F320/1 12.2. Accessing USB FIFO Space The upper 1k of XRAM functions as USB FIFO space. Figure 12.2 shows an expanded view of the FIFO space and user XRAM. FIFO space is accessed via USB FIFO registers; see for more information on accessing these FIFOs. The MOVX instruction should not be used to load or modify USB data in the FIFO space ...

Page 115

... MOVX command, effectively selecting a 256-byte page of RAM. The upper 5-bits are "don't cares", so the 2k address blocks are repeated modulo over the entire 64k external data memory address space. R/W R/W R/W R PGSEL2 PGSEL1 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value PGSEL0 00000000 Bit0 SFR Address: 0xAA 115 ...

Page 116

... C8051F320/1 116 Notes Rev. 1.1 ...

Page 117

... XTAL2 13.1. Programmable Internal Oscillator All C8051F320/1 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL register as defined by Equation 13.1, where is the frequency of the internal oscillator following a reset, ∆T is the change in internal oscillator period, and ...

Page 118

... C8051F320/1 On C8051F320/1 devices, OSCICL is factory calibrated to obtain a 12 MHz base frequency (f details oscillator programming for C8051F320/1 devices. Electrical specifications for the precision internal oscillator are given in Table 13.3 on page 126. Note that the system clock may be derived from the programmed internal oscil- lator divided defined by the IFCN bits in register OSCICN ...

Page 119

... Clock Recovery. R R/W R/W R IFCN1 Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W OSCCAL Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value IFCN0 00010100 Bit0 SFR Address: 0xB2 R/W Reset Value Variable Bit0 SFR Address: 0xB3 Section “15.4. USB 119 ...

Page 120

... C8051F320/1 13.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crystal/resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 13. MΩ resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal/resonator configuration ...

Page 121

... Assume VDD = 3.0 V and pF VDD ) = MHz 150 MHz If a frequency of roughly 150 kHz is desired, select the K Factor from the table in Figure 13 22 150 = 0.146 MHz, or 146 kHz Therefore, the XFCN value to use in this example is 011b. C8051F320/1 Rev. 1.1 121 ...

Page 122

... C8051F320/1 Figure 13.4. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal Oscillator is running and stable. Bits6-4: XOSCMD2-0: External Oscillator Mode Bits. ...

Page 123

... USB clock source Section 13.4 R/W R/W R/W R Bit4 Bit3 Bit2 Bit1 Selected Clock Internal Oscillator External Oscillator External Oscillator / 2 RESERVED Rev. 1.1 C8051F320/1 for details on selecting an exter- R/W Reset Value MULSEL 00000000 Bit0 SFR Address 0xB9 123 ...

Page 124

... C8051F320/1 13.4. System and USB Clock Selection The internal oscillator requires little start-up time and may be selected as the system or USB clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in register OSCXCN) is set to ‘ ...

Page 125

... Clock Multiplier Internal Oscillator / 2 External Oscillator External Oscillator / 2 External Oscillator / 3 External Oscillator / 4 RESERVED RESERVED Selected Clock Internal Oscillator (as determined by the IFCN bits in register OSCICN) External Oscillator 4x Clock Multiplier / 2 RESERVED Rev. 1.1 C8051F320/1 R/W Reset Value CLKSL 00000000 Bit0 SFR Address 0xA9 125 ...

Page 126

... C8051F320/1 Table 13.3. Internal Oscillator Electrical Characteristics -40°C to +85°C unless otherwise specified PARAMETER Internal Oscillator Frequency Internal Oscillator Supply Current (from VDD) † USB Clock Frequency † Applies only to external oscillator sources. 126 CONDITIONS MIN Reset Frequency 11.82 OSCICN Full Speed Mode 47 ...

Page 127

... PORT INPUT/OUTPUT Digital and analog resources are available through 25 I/O pins (C8051F320 I/O pins (C8051F321). Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 14.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins ...

Page 128

... C8051F320/1 Figure 14.2. Port I/O Cell Block Diagram /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT 128 VDD GND Analog Select Rev. 1.1 VDD (WEAK) PORT PAD ...

Page 129

... CEX1 CEX2 CEX3 CEX4 ECI P0SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins P1SKIP[0:7] Rev. 1.1 C8051F320 P2SKIP[0:3] 129 ...

Page 130

... C8051F320/1 Figure 14.4. Crossbar Priority Decoder with Crystal Pins Skipped P0 SF Signals PIN I TX0 RX0 SCK MISO MOSI NSS* SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI P0SKIP[0:7] Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins ...

Page 131

... Silicon Labs IDE software will determine the Port I/O pin-assignments based on the XBRn Register settings. Important Note: The Crossbar must be enabled to use Ports P0, P1, and P2.0-P2.3 as standard Port I/O in output mode. These Port output drivers are disabled while the Crossbar is disabled. P2.4-P2.7 and P3.0 always function as standard GPIO. C8051F320/1 Rev. 1.1 131 ...

Page 132

... C8051F320/1 Figure 14.5. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: CP1E: Comparator1 Output Enable 0: CP1 unavailable at Port pin. ...

Page 133

... CEX0, CEX1, CEX2, CEX3 routed to Port pins. 101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins. 110: Reserved. 111: Reserved. R/W R/W R/W R/W T0E ECIE PCA0ME Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value 00000000 Bit0 SFR Address: 0xE2 133 ...

Page 134

... C8051F320/1 14.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general pur- pose I/O. Ports3-0 are accessed through corresponding special function registers (SFRs) that are both byte address- able and bit addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin ...

Page 135

... R/W R/W P0.4 P0.3 P0.2 P0.1 Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value P0.0 11111111 Bit0 SFR Address: 0x80 (bit addressable) R/W Reset Value 11111111 Bit0 SFR Address: 0xF1 135 ...

Page 136

... C8051F320/1 Figure 14.9. P0MDOUT: Port0 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in register P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT) ...

Page 137

... R/W R/W P1.4 P1.3 P1.2 P1.1 Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value P1.0 11111111 Bit0 SFR Address: 0x90 (bit addressable) R/W Reset Value 11111111 Bit0 SFR Address: 0xF2 137 ...

Page 138

... C8051F320/1 Figure 14.13. P1MDOUT: Port1 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in register P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. Figure 14.14. P1SKIP: Port1 Skip Register ...

Page 139

... Read - Always reads ‘0’ if selected as analog input in register P2MDIN. Directly reads Port pin when configured as digital input. 0: P2.n pin is logic low. 1: P2.n pin is logic high. Note: P2.7-P2.4 only available on C8051F320 devices. Writes to these Ports do not require XBARE = ‘1’. Figure 14.16. P2MDIN: Port2 Input Mode Register R/W R/W ...

Page 140

... Bit6 Bit5 Bits7-0: Output Configuration Bits for P2.7-P2.0 (respectively): ignored if corresponding bit in register P2MDIN is logic 0. 0: Corresponding P2.n Output is open-drain. 1: Corresponding P2.n Output is push-pull. Note: P2.7-P2.4 only available on C8051F320 devices. Figure 14.18. P2SKIP: Port2 Skip Register R/W R/W R/W Bit7 Bit6 ...

Page 141

... R/W R/W P3.4 P3.3 P3.2 P3.1 Bit4 Bit3 Bit2 Bit1 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value P3.0 11111111 Bit0 SFR Address: 0xB0 (bit addressable) R/W Reset Value 00000001 Bit0 SFR Address: 0xF4 141 ...

Page 142

... C8051F320/1 Figure 14.21. P3MDOUT: Port3 Output Mode Register R/W R/W R Bit7 Bit6 Bit5 Bits7-1: UNUSED. Read = 0000000b; Write = don’t care. Bit0: Output Configuration Bit for P3.0; ignored if corresponding bit in register P3MDIN is logic 0. 0: Corresponding P3.n Output is open-drain. 1: Corresponding P3.n Output is push-pull. ...

Page 143

... UNIVERSAL SERIAL BUS CONTROLLER (USB0) C8051F320/1 devices include a complete Full/Low Speed USB function for USB peripheral implementations†. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mechanism for crystal-less operation. ...

Page 144

... C8051F320/1 15.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 15.1. Endpoint Addressing Scheme Endpoint Endpoint0 Endpoint1 Endpoint2 Endpoint3 15.2. USB Transceiver The USB Transceiver is configured via the USB0XCN register shown in Figure 15 ...

Page 145

... D+ signal currently at logic 1. Bit0: Dn: D- Signal Status This bit indicates the current logic level of the D- pin signal currently at logic signal currently at logic 1. R/W R/W R DFREC Dp Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320 Reset Value Dn 00000000 Bit0 SFR Address: 0xD7 145 ...

Page 146

... C8051F320/1 15.3. USB Register Access The USB0 controller registers listed in Table 15.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 15.3. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target endpoint num- ber. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the “ ...

Page 147

... USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the regis- ter indicated by the USBADDR bits. R/W R/W R/W R/W USBADDR Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value 00000000 Bit0 SFR Address: 0x96 147 ...

Page 148

... C8051F320/1 Figure 15.5. USB0DAT: USB0 Data Register R/W R/W R/W Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. ...

Page 149

... Endpoint IN Control / Status High Byte Endpoint OUT Control / Status Low Byte Endpoint OUT Control / Status High Byte Number of Received Bytes in Endpoint0 FIFO Endpoint OUT Packet Count Low Byte Endpoint OUT Packet Count High Byte Rev. 1.1 C8051F320/1 Page Number 157 158 159 160 160 ...

Page 150

... C8051F320/1 15.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in “ ...

Page 151

... FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint. When C8051F320/1 Configurable as IN, OUT, or both (Split ...

Page 152

... C8051F320/1 Split Mode is not enabled, double-buffering may be enabled for the entire endpoint FIFO. See Table 15.3 for a list of maximum packet sizes for each FIFO configuration. Table 15.3. FIFO Configurations Endpoint Split Mode Number Enabled 15.5.3. FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn register unloads one byte from the FIFO ...

Page 153

... Holds the 7-bit function address for USB0. This address should be written by software when the SET_ADDRESS standard device request is received on Endpoint0. The new address takes effect when the device request completes. R/W R/W R/W R/W Function Address Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value 00000000 Bit0 USB Address: 0x00 153 ...

Page 154

... C8051F320/1 15.7. Function Configuration and Control The USB register POWER (Figure 15.11) is used to configure and control USB0 at the device level (enable/disable, Reset/Suspend/Resume handling, etc.). USB Reset: The USBRST bit (POWER.3) is set to ‘1’ by hardware when Reset signaling is detected on the bus. Upon this detection, the following occur: 1 ...

Page 155

... Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. R/W R/W R/W USBINH USBRST RESUME SUSMD Bit4 Bit3 Bit2 Rev. 1.1 C8051F320/1 R R/W Reset Value SUSEN 00010000 Bit1 Bit0 USB Address: 0x01 155 ...

Page 156

... C8051F320/1 Figure 15.12. FRAMEL: USB0 Frame Number Low (USB Register Bit7 Bit6 Bit5 Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. Figure 15.13. FRAMEH: USB0 Frame Number High (USB Register Bit7 Bit6 Bit5 Bits7-3: Unused. Read = 0. Write = don’t care. ...

Page 157

... IN Endpoint 1 interrupt active. Bit0: EP0: Endpoint 0 Interrupt-pending Flag This bit is cleared when software reads the IN1INT register. 0: Endpoint 0 interrupt inactive. 1: Endpoint 0 interrupt active. 87 IN3 IN2 IN1 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320 Reset Value EP0 00000000 Bit0 USB Address: 0x02 157 ...

Page 158

... C8051F320/1 Figure 15.15. OUT1INT: USB0 Out Endpoint Interrupt (USB Register Bit7 Bit6 Bit5 Bits7-4: Unused. Read = 0000b. Write = don’t care. Bit3: OUT3: OUT Endpoint 3 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 3 interrupt inactive. 1: OUT Endpoint 3 interrupt active. ...

Page 159

... When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hardware when Suspend signaling is detected on the bus. This bit is cleared when software reads the CMINT register. 0: Suspend interrupt inactive. 1: Suspend interrupt active SOF RSTINT RSUINT Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320 Reset Value SUSINT 00000000 Bit0 USB Address: 0x06 159 ...

Page 160

... C8051F320/1 Figure 15.17. IN1IE: USB0 IN Endpoint Interrupt Enable (USB Register) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: Unused. Read = 0000b. Write = don’t care. Bit3: IN3E: IN Endpoint 3 Interrupt Enable 0: IN Endpoint 3 interrupt disabled Endpoint 3 interrupt enabled. Bit2: IN2E: IN Endpoint 2 Interrupt Enable 0: IN Endpoint 2 interrupt disabled. ...

Page 161

... DATAEND bit (E0CSR.3). The E0CNT register (Figure 15.21) holds the number of received data bytes in the Endpoint0 FIFO. R/W R/W R/W R/W - SOFE RSTINTE RSUINTE SUSINTE 00000110 Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value Bit0 USB Address: 0x0B 161 ...

Page 162

... C8051F320/1 Hardware will automatically detect protocol errors and send a STALL condition in response. Firmware may force a STALL condition to abort the current transfer. When a STALL condition is generated, the STSTL bit will be set to ‘1’ and an interrupt generated. The following conditions will cause hardware to generate a STALL condition: 1. The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to ‘ ...

Page 163

... Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when the expected amount of data has been received. The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firm- ware. An interrupt will be generated with the STSTL bit (E0CSR.2) set to ‘1’ after the STALL is transmitted. C8051F320/1 Rev. 1.1 163 ...

Page 164

... C8051F320/1 Figure 15.20. E0CSR: USB0 Endpoint0 Control (USB Register) R/W R/W R/W SSUEND SOPRDY SDSTL Bit7 Bit6 Bit5 Bit7: SSUEND: Serviced Setup End Write: Software should set this bit to ‘1’ after servicing a Setup End (bit SUEND) event. Hardware clears the SUEND bit when software writes ‘1’ to SSUEND. ...

Page 165

... E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a ‘1’ E0CNT Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320 Reset Value 00000000 Bit0 USB Address: 0x16 165 ...

Page 166

... C8051F320/1 15.11. Configuring Endpoints1-3 Endpoints1-3 are configured and controlled through their own sets of the following control/status registers: IN regis- ters EINCSRL and EINCSRH, and OUT registers EOUTCSRL and EOUTCSRH. Only one set of endpoint control/ status registers is mapped into the USB register address space at a time, defined by the contents of the INDEX regis- ter (Figure 15 ...

Page 167

... FIFO. The ISO Update feature ensures that any data packet written to the end- point FIFO will not be transmitted during the current frame; the packet will only be sent after a SOF signal has been received. C8051F320/1 Rev. 1.1 167 ...

Page 168

... C8051F320/1 Figure 15.22. EINCSRL: USB0 IN Endpoint Control High Byte (USB Register R/W - CLRDT STSTL Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bit6: CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’. ...

Page 169

... When SPLIT = ‘1’, the selected endpoint FIFO is split. The upper half of the selected FIFO is used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint. Bits1-0: Unused. Read = 00b; Write = don’t care. R R/W R/W - FCDT SPLIT Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320 Reset Value - - 00000000 Bit0 USB Address: 0x12 169 ...

Page 170

... C8051F320/1 15.13. Controlling Endpoints1-3 OUT Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in reg- ister EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware. ...

Page 171

... Hardware sets this bit to ‘1’ and generates an interrupt when a data packet is available. Software should clear this bit after each data packet is unloaded from the OUT endpoint FIFO R/W FLUSH DATERR OVRUN FIFOFUL Bit4 Bit3 Bit2 Rev. 1.1 C8051F320/1 R R/W Reset Value OPRDY 00000000 Bit1 Bit0 USB Address: 0x14 171 ...

Page 172

... C8051F320/1 Figure 15.25. EOUTCSRH: USB0 OUT Endpoint Control Low Byte (USB Register) R/W R/W R/W DBOEN ISO - Bit7 Bit6 Bit5 Bit7: DBOEN: Double-buffer Enable 0: Double-buffering disabled for the selected OUT endpoint. 1: Double-buffering enabled for the selected OUT endpoint. Bit6: ISO: Isochronous Transfer Enable This bit enables/disables isochronous transfers on the current endpoint ...

Page 173

... Driving High Driving Low Full Speed (D+ Pull-up) 1.425 Low Speed (D- Pull-up) Low Speed 75 Full Speed 4 Low Speed 75 Full Speed 4 | (D+) - (D-) | 0.2 0.8 Pullups Disabled Rev. 1.1 C8051F320/1 TYP MAX UNITS V 0 Ω 38 1.5 1.575 kΩ 300 ns 20 300 ns ...

Page 174

... C8051F320/1 174 Notes Rev. 1.1 ...

Page 175

... Request SCL Generation (Master Mode) SDA Control IRQ Generation 2 C serial bus. Reads and writes to the interface by the Overflow T1 Overflow 01 TMR2H Overflow 10 TMR2L Overflow 11 FILTER SCL Control Data Path SDA Control Control SMB0DAT FILTER Rev. 1.1 C8051F320/1 SCL Port I SDA N 175 ...

Page 176

... C8051F320/1 16.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents The I C-Bus and How to Use It (including specifications), Philips Semiconductor The I C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. ...

Page 177

... This arbitration scheme is non- destructive: one device always wins, and no data is lost. SLA5-0 R/W D7 ACK Data Byte Section “16.3.4. SCL High (SMBus Free) Timeout” on page Rev. 1.1 C8051F320/1 D6-0 NACK STOP 178). In the 177 ...

Page 178

... C8051F320/1 16.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I bilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line LOW to extend the clock low period, effectively decreasing the serial clock frequency ...

Page 179

... Slave event enable/disable • Clock source selection These options are selected in the SMB0CF register, as described in ter” on page 180. for more details on transmission sequences. Section “16.4.2. SMB0CN Control Register” Section “16.4.1. SMBus Configuration Regis- Rev. 1.1 C8051F320/1 Section 179 ...

Page 180

... C8051F320/1 16.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the INH bit. With slave events inhib- ited, the SMBus interface will still monitor the SCL and SDA pins ...

Page 181

... Free Timeout is detected, the interface will respond STOP was detected (an interrupt will be generated, and STO will be set). T SCL High Timeout High Minimum SDA Hold Time - 4 system clocks OR 3 system clocks † 11 system clocks 12 system clocks 178). The SMBus interface will force Timer 3 to reload while Rev. 1.1 C8051F320/1 is typically twice as HIGH 181 ...

Page 182

... C8051F320/1 Figure 16.5. SMB0CF: SMBus Clock/Configuration Register R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly monitors the SDA and SCL pins. 0: SMBus interface disabled. 1: SMBus interface enabled. ...

Page 183

... Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and the bus is stalled until software clears SI. Table 16.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 16.4 for SMBus status decoding using the SMB0CN register. C8051F320/1 Rev. 1.1 183 ...

Page 184

... C8051F320/1 Figure 16.6. SMB0CN: SMBus Control Register R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: SMBus operating in Master Mode. Bit6: TXMODE: SMBus Transmit Mode Indicator. ...

Page 185

... SI • A byte has been received. • A START or repeated START followed by a slave address + R/W has been received. • A STOP has been received. C8051F320/1 Cleared by Hardware When: • A STOP is generated. • Arbitration is lost. • A START is detected. • Arbitration is lost. • SMB0DAT is not written before the start of an SMBus frame. • ...

Page 186

... C8051F320/1 16.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is set. Software should not attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0, as the interface may be in the process of shifting a byte of data into or out of the register ...

Page 187

... ACK cycle in this mode. Figure 16.8. Typical Master Transmitter Sequence S SLA Interrupt Received by SMBus Interface Transmitted by SMBus Interface W A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev. 1.1 C8051F320 Interrupt 187 ...

Page 188

... C8051F320/1 16.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial data. After each byte is received, ACKRQ is set to ‘ ...

Page 189

... Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode. Figure 16.10. Typical Slave Receiver Sequence S SLA W Interrupt Received by SMBus Interface Transmitted by SMBus Interface A Data Byte A Data Byte Interrupt Interrupt S = START P = STOP A = ACK W = WRITE SLA = Slave Address Rev. 1.1 C8051F320/1 Interrupt A P 189 ...

Page 190

... C8051F320/1 16.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave Transmitter Mode, an interrupt is generated and the ACKRQ bit is set ...

Page 191

... ACK received. 1100 master data byte was received; ACK requested. 1000 C8051F320/1 TYPICAL RESPONSE OPTIONS Load slave address + R/W into SMB0DAT. Set STA to restart transfer. Abort transfer. Load next data byte into SMB0DAT. End transfer with STOP. End transfer with STOP and start another transfer ...

Page 192

... C8051F320/1 Table 16.4. SMBus Status Decoding VALUES READ CURRENT SMBUS STATE A slave byte was transmitted; NACK received. A slave byte was transmitted; ACK 0100 received. A Slave byte was transmitted; error detected. A STOP was detected while an 0101 addressed Slave Transmitter. A slave address was received; ACK requested ...

Page 193

... CLR Zero Detector Shift Data Tx Control Send Tx IRQ SCON TI Serial Port Interrupt RI Rx IRQ Rx Control Load SBUF Shift 0x1FF RB8 Input Shift Register (9 bits) Load SBUF SBUF (RX Latch) Read SBUF SFR Bus Rev. 1.1 C8051F320/1 Section TX Crossbar Port I/O RX Crossbar 193 ...

Page 194

... C8051F320/1 17.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 17.2), which is not user-accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates. The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1) ...

Page 195

... If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An interrupt will occur if enabled when either TI0 or RI0 is set. Figure 17.4. 8-Bit UART Timing Diagram MARK START D0 BIT SPACE BIT TIMES BIT SAMPLING TX RS-232 RS-232 C8051Fxxx LEVEL RX XLTR MCU C8051Fxxx Rev. 1.1 C8051F320/1 STOP D6 D7 BIT 195 ...

Page 196

... C8051F320/1 17.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB80 (SCON0.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in register PSW) for error detection, or used in multiprocessor communications ...

Page 197

... Figure 17.6. UART Multi-Processor Mode Interconnect Diagram Master Slave Device Device Slave Slave Device Device Rev. 1.1 C8051F320 197 ...

Page 198

... C8051F320/1 Figure 17.7. SCON0: Serial Port 0 Control Register R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit UART with Variable Baud Rate. Bit6: UNUSED. Read = 1b. Write = don’ ...

Page 199

... SBUF0, it goes to the transmit shift register and is held for serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of SBUF0 returns the contents of the receive latch. R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 Rev. 1.1 C8051F320/1 R/W Reset Value 00000000 Bit0 0x99 SFR Address: 199 ...

Page 200

... C8051F320/1 Table 17.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator Frequency: 24.5 MHz Target Baud Rate Baud Rate % Error (bps) 230400 -0.32% 115200 -0.32% 57600 0.15% 28800 -0.32% 14400 0.15% 9600 -0.32% 2400 -0.32% 1200 0.15% † SCA1-SCA0 and T1M bit definitions can be found in Table 17 ...

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