C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 247

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Note that the 8-bit offset held in PCA0CPH4 is compared to the upper byte of the 16-bit PCA counter. This offset
value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the first PCA0L
overflow occurs, depending on the value of the PCA0L when the update is performed. The total offset is then given
(in PCA clocks) by Equation 20.4, where PCA0L is the value of the PCA0L register at the time of the update.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH4 and PCA0H. Soft-
ware may force a WDT reset by writing a ‘1’ to the CCF4 flag (PCA0CN.4) while the WDT is enabled.
20.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog timer is
enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the WDT cannot be
disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by 12,
PCA0L defaults to 0x00, and PCA0CPL4 defaults to 0x00. Using Equation 20.4, this results in a WDT timeout inter-
val of 256 system clock cycles. Table 20.3 lists some example timeout intervals for typical system clocks.
1.
2.
3.
4.
mode).
5.
6.
to ‘1’.
Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2-CPS0 bits).
Load PCA0CPL4 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
Enable the WDT by setting the WDTE bit to ‘1’.
(optional) Lock the WDT (prevent WDT disable until the next system reset) by setting the WDLCK bit
†
0x00 at the update time.
††
Assumes SYSCLK / 12 as the PCA clock source, and a PCA0L value of
Internal oscillator reset frequency.
System Clock (Hz)
Equation 20.4. Watchdog Timer Offset in PCA Clocks
Offset
Table 20.3. Watchdog Timer Timeout Intervals
12,000,000
12,000,000
12,000,000
18,432,000
18,432,000
18,432,000
11,059,200
11,059,200
11,059,200
4,000,000
4,000,000
4,000,000
32,000
32,000
32,000
=
(
256 PCA0CPL4
×
PCA0CPL4
255
128
255
128
255
128
255
128
255
128
32
32
32
32
32
Rev. 1.1
)
+
(
256 PCA0L
Timeout Interval (ms)
–
24,576.0
12,384.0
3,168.0
196.6
65.5
33.0
42.7
21.5
71.1
35.8
99.1
25.3
8.4
5.5
9.2
)
†
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