C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 249

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit7:
Bit6:
Bit5:
Bit4:
Bits3-1:
Bit0:
Note: When the WDTE bit is set to ‘1’, the PCA0MD register cannot be modified. To change the contents
CIDL
R/W
Bit7
CIDL: PCA Counter/Timer Idle Control.
Specifies PCA behavior when CPU is in Idle Mode.
0: PCA continues to function normally while the system controller is in Idle Mode.
1: PCA operation is suspended while the system controller is in Idle Mode.
WDTE: Watchdog Timer Enable
If this bit is set, PCA Module 4 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA Module 4 enabled as Watchdog Timer.
WDLCK: Watchdog Timer Lock
This bit enables and locks the Watchdog Timer. When WDLCK is set to ‘1’, the Watchdog Timer may
not be disabled until the next system reset.
0: Watchdog Timer unlocked.
1: Watchdog Timer enabled and locked.
UNUSED. Read = 0b, Write = don't care.
CPS2-CPS0: PCA Counter/Timer Pulse Select.
These bits select the timebase source for the PCA counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
of the PCA0MD register, the Watchdog Timer must first be disabled.
†
External oscillator source divided by 8 is synchronized with the system clock.
CPS2
WDTE
0
0
0
0
1
1
1
1
R/W
Bit6
CPS1
WDLCK
0
0
1
1
0
0
1
1
Figure 20.12. PCA0MD: PCA Mode Register
R/W
Bit5
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
-
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
System clock
External clock divided by 8
Reserved
Reserved
CPS2
R/W
Bit3
Rev. 1.1
CPS1
R/W
Bit2
.
†
CPS0
R/W
Bit1
C8051F320/1
ECF
R/W
Bit0
SFR Address:
01000000
Reset Value
0xD9
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