C8051F320 Silicon Laboratories Inc, C8051F320 Datasheet - Page 170

• Manufacturer Part Number: C8051F320
• Description: IC 8051 MCU 16K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F320

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

C8051F320/1
15.13. Controlling Endpoints1-3 OUT
Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can be used
for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to the ISO bit in reg-
ister EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 OUT interrupt may be generated by the following:
15.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode
When the ISO bit (EOUTCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt mode. Once an endpoint has
been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0 SET_INTERFACE com-
mand), hardware will set the OPRDY bit (EOUTCSRL.0) to ‘1’ and generate an interrupt upon reception of an OUT
token and data packet. The number of bytes in the current OUT data packet (the packet ready to be unloaded from the
FIFO) is given in the EOUTCNTH and EOUTCNTL registers. In response to this interrupt, firmware should unload
the data packet from the OUT FIFO and reset the OPRDY bit to ‘0’.
A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While
SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware generates a
STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The STSTL bit must
be reset to ‘0’ by firmware.
Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO. Note that if double buffering is
enabled for the target endpoint, it is possible for two packets to be ready in the OUT FIFO at a time. In this case, hard-
ware will set OPRDY to ‘1’ immediately after firmware unloads the first packet and resets OPRDY to ‘0’. A second
interrupt will be generated in this case.
15.13.2.Endpoints1-3 OUT Isochronous Mode
When the ISO bit (EOUTCSRH.6) is set to ‘1’, the target endpoint operates in Isochronous (ISO) mode. Once an end-
point has been configured for ISO OUT mode, the host will send exactly one data per USB frame; the location of the
data packet within each frame may vary, however. Because of this, it is recommended that double buffering be
enabled for ISO OUT endpoints.
Each time a data packet is received, hardware will load the received data packet into the endpoint FIFO, set the
OPRDY bit (EOUTCSRL.0) to ‘1’, and generate an interrupt (if enabled). Firmware would typically use this interrupt
to unload the data packet from the endpoint FIFO and reset the OPRDY bit to ‘0’.
If a data packet is received when there is no room in the endpoint FIFO, an interrupt will be generated and the
OVRUN bit (EOUTCSRL.2) set to ‘1’. If USB0 receives an ISO data packet with a CRC error, the data packet will be
loaded into the endpoint FIFO, OPRDY will be set to ‘1’, an interrupt (if enabled) will be generated, and the
DATAERR bit (EOUTCSRL.3) will be set to ‘1’. Software should check the DATAERR bit each time a data packet is
unloaded from an ISO OUT endpoint FIFO.
170
1.
2.
Hardware sets the OPRDY bit (EINCSRL.0) to ‘1’.
Hardware generates a STALL condition.
Rev. 1.1