TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 131

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TMPM362F10FG

Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet

Specifications of TMPM362F10FG

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
 Details
Other names
Q5704184A

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
Part Number:
TMPM362F10FG(C)
Manufacturer:
Toshiba
Quantity:
10 000
7.6.3
31
30-28
27-26
25
24
23
22-20
19-18
17
16
15
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
7.6.3.1
EMCG3[2:0]
EMST3[1:0]
INT3EN
EMCG2[2:0]
EMST2[1:0]
INT2EN
Clock generator registers
Bit Symbol
CGIMCGA (CG Interrupt Mode Control Register A)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R
R
R/W
R
R/W
R
R
R/W
R
Type
30
22
14
0
0
0
6
0
Read as 0,
active level setting of INT3 standby clear request. (101 to 111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edge
active level of INT3 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Reads as undefined.
INT3 clear input
0: Disable
1: Enable
Read as 0,
active level setting of INT2 standby clear request. (101 to 111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edge
active level of INT2 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Reads as undefined.
INT2 clear input
0:Disable
1: Enable
Read as 0,
EMCG3
EMCG2
EMCG1
EMCG0
29
21
13
1
1
1
5
1
Page 107
28
20
12
0
0
0
4
0
27
19
11
Function
0
0
0
3
0
EMST3
EMST2
EMST1
EMST0
26
18
10
0
0
0
2
0
Undefined
Undefined
Undefined
Undefined
25
17
9
1
-
-
-
-
TMPM362F10FG
INT3EN
INT2EN
INT1EN
INT0EN
24
16
0
0
8
0
0
0

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