TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 605
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 605 of 744
- Download datasheet (8Mb)
20.3.4
31-8
7
6
5
4-3
2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
−
EOCFN
ADBFN
−
ITM[1:0]
REPEAT
SCAN
ADS
Note 1: This bit is "0" cleared when it is read.
Note 2: It is valid only when it’s specified in the fixed channel repeat mode (<REPEAT> ="1", <SCAN> = "0").
Note 3: Conversion must be started after setting the mode.
Note 4: When DMA transfer is executed by utilizing AD conversion completion interrupts, perform software reset first.
Bit Symbol
ADMOD0 (Mode Control Register 0)
EOCFN
31
23
15
0
0
0
7
0
-
-
-
Then startup a DMA operation (DMA request wait mode), and start ADC setting.
R
R
R
R
R/W
R/W
R/W
R/W
Type
ADBFN
30
22
14
0
0
0
6
0
Read as "0".
Normal AD conversion completion flag (note1)
0: Before or during conversion
1: Completion
Normal AD conversion busy flag
0: Conversion stop
1: During conversion
Read as "0".
Specify interrupt in fixed channel repeat conversion mode (refer to the table below and note 2)
Specify repeat mode
0: Single conversion mode
1: Repeat conversion mode
Specify scan mode
0: Fixed channel mode
1: Channel scan mode
Start AD conversion start (note3)
0: Don't care
1: Start conversion
Always read as "0".
-
-
-
29
21
13
0
0
0
5
0
-
-
-
-
Page 581
28
20
12
0
0
0
4
0
-
-
-
Specify AD conversion interrupt in fixed channel repeat conversion
<ITM[1:0]>
ITM
00
01
10
11
27
19
11
Function
0
0
0
3
0
-
-
-
Generate interrupt once every single conversion.
Generate interrupt once every 4 conversions.
Generate interrupt once every 8 conversions.
Setting prohibited
REPEAT
Fixed channel repeat conversion mode
26
18
10
<SCAN> = "0", <REPEAT> = "1"
0
0
0
2
0
-
-
-
mode
SCAN
25
17
0
0
9
0
1
0
-
-
-
TMPM362F10FG
ADS
24
16
0
0
8
0
0
0
-
-
-
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