TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 561

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

16.4
16.4.1
16.4.1.1
16.4.1.2
Data reception completed by dstecting the max data bit cycle
Operation Description
tion interrupt. When a leader detection interrupt occurs, RMCxRSTAT<RMCRLIF> bit is set.
in RMCxRBUF1, RMCxRBUF2 and RMCxRBUF3 registers up to 72 bits. By setting RMCxRCR2<
RMCEDIEN> bit, a remote control signal input falling edge interrupt can be generated in each falling
edge of data bit. When a remote control signal input falling edge interrupt is generated, RMCxRSTAT<
RMCEDIF > bit is set.
ue, and then, an interrupt occurs. If <RMCEND1>, <RMCEND2> nad <RMCEND3> of the register
RMCxEND1, RMCxEND2 and RMCEND3 have been configured, data reception stops and an interrupt oc-
curs only in the case that the number of bits received before maximum data bit cycle is detected. The con-
dition of RMC can be checked by reading the remote control receive status register.
ception without detecting a leader.
is overwritten by the next one.
Reception of Remote Control Signal
Waiting for leader
A remote control signal is sampled by using low-speed 32.768kHz clock (fs).
RMC set RMCxRSTAT<RMCRLDR> bit when a leader is detected.
At this time, if you set the RMCxRCR2<RMCLIEN> bit, leader detection will generate a leader detec-
After the leader detecting, each data bit is determined as "0" or "1" in sequence. The results are stored
Data reception stops when the maximum data bit cycle is detected annd low-width matches the setting val-
To check the status of RMC if reception is completed, read the remote control receive status register.
On completion of reception, RMC is waiting for the next leader.
By setting RMC to receive a signal without a leader, RMC recognizes the received as data and starts re-
If the next data reception is completed before reading the preceding received data, the preceding data
Sampling clock
Basic operation
Detecting leader
Capable of receiving data up to 72bit
Page 537
Specified period of a maximum data bit cycle
The maximum data bit cycle interrupt
TMPM362F10FG
Waiting for leader