TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 680

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

22.2
Operation Mode
22.2.10.4
See Table 22-9 for the transfer format of this command.
Chip and Protection Bit Erase Command
1. The processing of the 1st and 2nd bytes are the same as for the RAM Transfer command.
2. From the Controller to the TMPM362F10FG
3. From TMPM362F10FG to the Controller
4. From the controller to the TMPM362F10FG
5. From TMPM362F10FG to the Controller
6. From TMPM362F10FG to the Controller
for the Show Product Information command is 0x40.
sponse to the 3rd byte.
ror. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the com-
mand wait state again. In this case, the upper four bits of the acknowledge response are unde-
fined - they hold the same values as the upper four bits of the previously issued command.
echoes it back to the controller. When the Show Flash Memory Sum command was received,
the boot program echoes back a value of 0x40. If the 3rd byte is not a valid command, the
boot program sends back 0xX1 (bit 0) to the controller and returns to the state in which it
waits for a command (the third byte) again. In this case, the upper four bits of the acknowl-
edge response are undefined - they hold the same values as the upper four bits of the previous-
ly issued command.
mand code (0x54).
sponse to the 5th byte.
ror. If there was a receive error, the boot program transmits 0xX8 (bit 3) and returns to the com-
mand wait state again. In this case, the upper four bits of the acknowledge response are unde-
fined - they hold the same values as the upper four bits of the previously issued command.
oes it back to the controller. When the Chip and Protection Erase command was received, the
boot program echoes back a value of 0x54 and then branches to the Chip Erase routine. If the
5th byte is not a valid command, the boot program sends back 0xX1 (bit 0) to the controller
and returns to the state in which it waits for a command (the third byte) again. In this case,
the upper four bits of the acknowledge response are undefined - they hold the same values as
the upper four bits of the previously issued command.
The 3rd byte, which the target board receives from the controller, is a command. The code
The 4th byte, transmitted from the target board to the controller, is an acknowledge re-
Before sending back the acknowledge response, the boot program checks for a receive er-
If the 3rd byte is equal to any of the command codes listed in Table 22-4, the boot program
The 5th byte, transmitted from the target board to the controller, is the Chip Erase Enable com-
The 6th byte, transmitted from the target board to the controller, is an acknowledge re-
Before sending back the acknowledge response, the boot program checks for a receive er-
If the 5th byte is equal to any of the command codes to enable erasing, the boot program ech-
The 7th byte indicates whether the Chip Erase command is normally completed or not.
At normal completion, completion code (0x4F) is sent.
When an error was detected, error code (0x4C) is sent.
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TMPM362F10FG