TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 465
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 465 of 744
- Download datasheet (8Mb)
13.6.1
Figure 13-3 SSI frame format (transmission/reception during continuous transfer)
Figure 13-2 SSI frame format (transmission/reception during single transfer)
line SPDO becomes Hi-Z. When data is written in the transmit FIFO, the master outputs "High" pulses of 1
SPCLK to the SPFSS line. The transmitted data will be transferred from the transmit FIFO to the transmit se-
rial shift register. Data of 4 to 16 bits will be output from the SPDO pin at the next rising edge of SPCLK.
SPCLK. The received data will be transferred from the serial shift register into the receive FIFO at the rising
edge of SPCLK after its LSB data is latched.
Note 1: When transmission is disable , SPDO terminal doesn't output and is high impedance status. This terminal needs
Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance sta-
In this mode, the SSP is in idle state, SPCLK and SPFSS are forcedly set to "Low", and the transmit data
Likewise, the received data will be input starting from the MSB to the SPDI pin at the falling edge of
SSI frame format
to add suitable pull-up/down resistance to valid the voltage level.
tus, this terminal needs to add suitable pull-up/down resistance to valid the voltage level.
SPDO
SPFSS
SPDI
SPCLK
SPDO
SPDI
SPCLK
SPFSS
Hi-Z(Note1
Hi-Z(Note2
LSB
LSB
MSB
MSB
MSB
MSB
Page 441
4 to 16bit
4 to 16 bit
LSB
LSB
LSB
LSB
MSB
MSB
Hi-Z(Note2
Hi-Z(Note1
TMPM362F10FG
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