TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 65

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

6.3
6.3.1
6.3.2
Clock control
IDLE2, SLEEP, STOP).
or X2 pin.
Clock System Block Diagram
Initial Values after Reset
Each clock is defined as follows :
The high-speed clock fc and the prescaler clock φT0 are dividable as follows.
CPU uses the following clocks. HCLK and FCLK stop in the low power consumption mode (IDLE1,
Reset operation initializes the clock configuration as follows.
Reset operation causes all the clock configurations excluding the low-speed clock (fs) to be the same as fosc.
For example, reset operation configures fsys as 10MHz when a 10MHz oscillator is connected to the X1
High-speed oscillator
Low-speed oscillator
PLL (Phase locked loop circuit)
High-speed clock gear
fosc
fs
fpll
fc
fgear
fsys
fperiph
φT0
High-speed clock
Prescaler clock
HCLK,FCLK
STCLK (Systick timer)
fc = fosc
fsys = fosc
φT0 = fosc
: Clock input from the X1 and X2 pins
: Clock input from the XT1 and XT2 pins (low-speed clock)
: Clock quadrupled or octupled by PLL
: Clock specified by CGPLLSEL<PLLSEL> (high-speed clock)
: Clock specified by CGSYSCR<GEAR[2:0]>
: Clock specified by CGCKSEL<SYSCK> (system clock)
: Clock specified by CGSYSCR<FPSEL0>
: Clock specified by CGSYSCR<FPSEL1> (Prescaler clock)
: fc, fc/2, fc/4, fc/8
: fs, fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32
: fsys
: fosc/32
: oscillating
: oscillating
: stop
: fc (no frequency dividing)
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TMPM362F10FG