TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 446

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.16
Operation in Each Mode
12.16.4.2
Protocol
1. Select the 9-bit UART mode for the master and slave controllers.
2. Set SCxMOD<WU> to "1" for the slave controllers to make them ready to receive data.
3. The master controller is to transmit a single frame of data that includes the slave controller se-
4. Each slave controller receives the above data frame; if the code received matches with the con-
5. The master controller transmits data to the designated slave controller (the controller of which
6. The slave controllers with the <WU> bit set to "1" ignore the receive data because the most sig-
lect code (8 bits). In this, the most significant bit (bit 8) <TB8> must be set to "1".
troller’s own select code, it clears the <WU> bit to "0".
SCxMOD<WU> bit is cleared to "0"). In this, the most significant bit (bit 8) <TB8> must be
set to "0".
nificant bit (bit 8) <RB8> is set to "0" and thus no interrupt (INTRXx) is generated.Also, the
slave controller with the <WU> bit set to "0" can transmit data to the master controller to in-
form that the data has been successfully received.
start
start
bit 0
bit 0
Select cide of the slave controller
1
1
2
2
Data
3
3
Page 422
4
4
5
5
6
6
7
7
bit 8
"1"
"0"
8
stop
stop
TMPM362F10FG