TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 672
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TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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22.2
Operation Mode
Table 22-9 Transfer Format for the Chip and Protection Bit Erase Command
Boot
ROM
22.2.9.4
1 byte
2 byte
3 byte
4 byte
5 byte
6 byte
7 byte
8 byte
Note 1: In I/O Interface mode, the baud rate for the transfers of the first and second byte must be 1/16 of the
Note 2: In case of any negative acknowledge, the boot program returns to a state in which it waits for a com-
Byte
Chip Erase and Protect Bit Erase
desired baud rate.
mand code (3rd byte). In I/O Interface mode, if a communication error occurs, a negative acknowl-
edge does not occur.
Serial operation mode and baud rate
For UART mode : 0x86
For I/O Interface mode : 0x30
−
Command code (0x40)
−
Chip erase command code (0x54)
−
−
(Wait for the next command code.)
Data Transferred from the Controller to the
TMPM362F10FG
Page 648
Desired baud
rate (Note 1)
Baud rate
−
ACK for the serial operation mode byte
・For UART mode
- Normal acknowledge : 0x86
(The boot program aborts if the baud rate can
not be set correctly.)
・For I/O Interface mode
- Normal acknowledge :0x30
−
ACK for the command code byte (Note 2)
- Normal acknowledge : 0x10
- Negative acknowledge : 0xX1
- Communication error : 0xX8
−
ACK for the command code byte (Note 2)
- Normal acknowledge : 0x10
- Negative acknowledge : 0xX1
- Communication error : 0xX8
ACK for the chip erase command code byte
- Normal acknowledge : 0x4F
- Negative acknowledge : 0x4C
−
Data Transferred from the TMPM362F10FG to
the Controller
TMPM362F10FG
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