TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 429
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TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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12.13
pin and to prevent overrun errors. This function can be enabled or disabled by SCxMOD0<CTSE>.
mission is suspended until CTS pin returns to the "Low" level. However in this case, the INTTXx interrupt is gen-
erated in the normal timing, the next transmit data is written in the transmit buffer, and it waits until it is ready to
transmit data.
the port for the RTS function. By setting the port to "High" level upon completion of data reception (in the re-
ceive interrupt routine), the transmit side can be requested to suspend data transmission.
Data write to transmit
buffer or shift register
Note 1: If the CTS signal is set to "High" during transmission, the next data transmission is suspended after
Note 2: Data transmission starts on the first falling edge of the TXDCLK clock after CTS is set to "Low".
The function of the handshake is to enable frame-by-frame data transmission by using the CTS (Clear to send)
When the CTS pin is set to "High" level, the current data transmission can be completed but the next data trans-
Although no RTS pin is provided, a handshake control function can easily implemented by assigning one bit of
Handshake Function
TXDCLK
the current transmission is completed.
SIOCLK
CTS
TXD
a
Transmit side
Transmission is
suspended during
this period.
Figure 12-8 Handshake Function
Figure 12-9 CTS Signal timing
TXD
CTS
13 14 15 16
b
Page 405
1
2
Start bit
RXD
RTS (Any port)
3
Receive side
14 15 16
TMPM362F10FG
1
2
Bit 0
3
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