TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 506
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
- Current page: 506 of 744
- Download datasheet (8Mb)
14.8
Control in SIO mode
14.8.2
14.8.2.1
INTSBIx interrupt
SBIxCR1<SIOM[1:0]>.
SBIxCR1
SBIxDBR
SBIxCR1
SBIxDBR
The transmit mode, the receive mode or the transmit/receive mode can be selected by programming
ta is moved from SBIxDBR to a shift register and output to the SO pin, with the least-significant bit
(LSB) first, in synchronization with the serial clock. Once the transmit data is transferred to the shift regis-
ter, SBIxDBR becomes empty, and the INTSBIx (buffer-empty) interrupt is generated, requesting the
next transmit data.
next data is not loaded after the 8-bit data has been fully transmitted. The wait state will be cleared when
SBIxDBR is loaded with the next transmit data.
ted. Therefore, the data transfer rate varies depending on the maximum latency between when the inter-
rupt request is generated and when SBIxDBR is loaded with data in the interrupt service program.
put in a period from setting SBIxSR<SIOF> to "1" to the falling edge of SCK.
TSBIx interrupt service program. If <SIOS> is cleared, remaining data is output before transmission
ends. The program checks SBIxSR<SIOF> to determine whether transmission has come to an end.
<SIOF> is cleared to "0" at the end of transmission. If <SIOINH> is set to "1", the transmission is abor-
ted immediately and <SIOF> is cleared to "0".
does not be cleared to "0" before next data shifting, SBI output dummy data and stopped.
Transfer Modes
Set the control register to the transmit mode and write the transmit data to SBIxDBR.
After writing the transmit data, writing "1" to SBIxCR1<SIOS> starts the transmission. The transmit da-
In the internal clock mode, the serial clock will be stopped and automatically enter the wait state, if
In the external clock mode, SBIxDBR must be loaded with data before the next data shift operation is star-
At the beginning of transmission, the same value as in the last bit of the previously transmitted data is out-
Transmission can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the IN-
When in the external clock mode, <SIOS> must be cleared to "0" before next data shifting. If <SIOS>
8-bit transmit mode
←
←
←
←
7
0
X
1
X
6
1
X
0
X
5
0
X
0
X
4
0
X
0
X
3
0
X
0
X
2
X
X
X
X
1
X
X
X
X
Page 482
0
X
X
X
X
Selects the transmit mode.
Writes the transmit data.
Starts transmission.
Writes the transmit data.
TMPM362F10FG
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