ispPAC-CLK5620AV-01TN100I Lattice, ispPAC-CLK5620AV-01TN100I Datasheet - Page 17

• Manufacturer Part Number: ispPAC-CLK5620AV-01TN100I
• Description: Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
• Manufacturer: Lattice

Specifications of ispPAC-CLK5620AV-01TN100I

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Typical Performance Characteristics (Cont.)
Detailed Description
PLL Subsystem
The ispClock5600A provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig-
nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the
PLL are an edge-sensitive phase detector, a programmable loop filter, and a high-speed voltage-controlled oscilla-
tor (VCO). Additionally, a set of programmable input, output and feedback dividers (M, N, V[1..5]) is provided to
support the synthesis of different output frequencies.
Phase/Frequency Detector
The ispClock5600A provides an edge-sensitive phase/frequency detector (PFD), which means that the device will
function properly over a wide range of input clock reference duty cycles. It is only necessary that the input refer-
ence clock meet specified minimum HIGH and LOW times (t
the PFD. The PFD’s output is of a classical charge-pump type, outputting charge packets which are then integrated
by the PLL‘s loop filter.
A lock-detection feature is also associated with the PFD. When the ispClock5600A is in a LOCKED state, the
LOCK output pin goes LOW. The lock detector has two operating modes: Phase Lock Detect mode and Frequency
60
55
50
45
40
35
30
80
70
60
50
40
30
20
10
0
*PFD = Phase/Frequency Detector
320
320
V = 16
V = 8
V = 4
Typical Period Jitter vs. VCO Frequency
Typical Phase Jitter vs. VCO Frequency
370
370
V = 32
420
420
VCO Frequency
VCO Frequency
V = 4, 8, 16, 32
PFD* = 80 MHz
PFD = 80 MHz
470
470
520
520
(MHz)
(MHz)
570
570
620
620
800
800
1-17
CLOCKHI,
140
120
100
80
60
40
20
0
320
Typical Cycle-Cycle Jitter vs. VCO Frequency
V = 4
V = 32
V = 8
t
370
CLOCKLO
ispClock5600A Family Data Sheet
V = 16
420
VCO Frequency
) for it to be properly recognized by
PFD = 80 MHz
470
520
(MHz)
570
620
800