ispPAC-CLK5620AV-01TN100I Lattice, ispPAC-CLK5620AV-01TN100I Datasheet - Page 31

• Manufacturer Part Number: ispPAC-CLK5620AV-01TN100I
• Description: Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
• Manufacturer: Lattice

Specifications of ispPAC-CLK5620AV-01TN100I

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 1-26. Output Timing Adders for Logic Type (a) and Output Slew Rate (b)
Similarly, when one changes the slew rate of an output, the output slew rate adders (t
the resulting skew. In this case, the fastest slew setting (1) is used as the baseline against which other slews are
measured. For example, in the case of outputs configured to the same logic type (e.g. LVCMOS 1.8V), if one output
is set to the fastest slew rate (1, t
660ps of skew between the two outputs, as shown in Figure 1-26b.
Static Phase Offset and Input-Output Skew
The ispClock5600A’s external feedback inputs can be used to obtain near-zero effective delays from the clock ref-
erence input pins to a designated output pin. In external feedback mode (Figure 1-27) the PLL will attempt to force
the output phase so that the rising edge phase (t φ) at the feedback input matches the rising edge phase at the ref-
erence input. The residual error between the two is specified as the static phase error. Note that any propagation
delays (t
the output. For this reason, if zero input-to-output delays are required in external feedback mode, the length of the
signal path between the output pin and the feedback pin should be minimized.
Figure 1-27. External Feedback Mode and Timing Relationships (Input, Output and Feedback Use the Same
Logic Standard)
LVDS Output
(T
LVTTL Output
(T
FBK
IOO
IOO
) in the external feedback path drive the phase of the output signal backwards in time as measured at
= 0)
= 0.395ns)
Input Reference Clock
BANK OUTPUT
FEEDBACK
(a)
OUTPUT
IOS
0.395ns
REF
FBK
= 0ps), and another set to slew rate 3 (t
FBK
REF
t
SKEW
ispClock5600A
Delay = t
FEEDBACK OUTPUT
t
1-31
SKEW
t
t
LVCMOS Output
(Slew rate=1)
LVCMOS Output
(Slew rate=3)
FBK
φ
BANK OUTPUT
FBK
ispClock5600A Family Data Sheet
IOS
= 660ps), then one could expect
(b)
660ps
IOS
) can be used to predict