ispPAC-CLK5620AV-01TN100I Lattice, ispPAC-CLK5620AV-01TN100I Datasheet - Page 36

• Manufacturer Part Number: ispPAC-CLK5620AV-01TN100I
• Description: Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
• Manufacturer: Lattice

Specifications of ispPAC-CLK5620AV-01TN100I

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Evaluation Fixture
Included in the basic ispClock5600A Design Kit is an engineering prototype board that can be connected to the
parallel port of a PC using a Lattice ispDOWNLOAD
ispClock5600A and can be used in real time to check circuit operation as part of the design process. Input and out-
put connections (SMA connectors for all RF signals) are provided to aid in the evaluation of the ispClock5600A for
a given application. (Figure 1-30).
Figure 1-30. Download from a PC
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5600A is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispClock5600A both as a serial programming interface, and for boundary scan
test purposes. A brief description of the ispClock5600A JTAG interface follows. For complete details of the refer-
ence specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispClock5600A. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
E
are defined that access all data registers and perform other internal control operations. For compatibility between
compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally spec-
ified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manu-
facturer. The two required registers are the bypass and boundary-scan registers. Figure 1-31 shows how the
instruction and various data registers are organized in an ispClock5600A.
2
CMOS cells. It is these non-volatile cells that store the configuration of the ispClock5600A. A set of instructions
PAC-SYSTEMCLK5620A
PACCLK5620A-EV
Part Number
PAC-Designer
Software
Complete system kit, evaluation board, ispDOWNLOAD cable and software.
Evaluation board only, with components, fully assembled.
1-36
®
cable. It demonstrates proper layout techniques for the
ispDownload
Cable (6')
Description
ispClock5600A Family Data Sheet
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ispClock5600A
Circuitry
System
Device
Other