ispPAC-CLK5620AV-01TN100I Lattice, ispPAC-CLK5620AV-01TN100I Datasheet - Page 9

• Manufacturer Part Number: ispPAC-CLK5620AV-01TN100I
• Description: Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
• Manufacturer: Lattice

Specifications of ispPAC-CLK5620AV-01TN100I

• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Output Rise and Fall Times – Typical Values
Output Test Loads
Figures 1-3-1-5 show the equivalent termination loads used to measure rise/fall times, output timing adders and
other selected parameters as noted in the various tables of this data sheet.
Figure 1-3. CMOS Termination Load
Figure 1-4. eHSTL/HSTL/SSTL Termination Load
LVTTL
LVCMOS 1.8V
LVCMOS 2.5V
LVCMOS 3.3V
SSTL18
SSTL2
SSTL3
HSTL
eHSTL
LVDS
LVPECL
1. See Figures 1-3-1-5 for test conditions.
2. Measured between 20% and 80% points.
3. Only the ‘fastest’ slew rate is available in LVDS and LVPECL modes.
Output Type
3
3
ispCLOCK
Slew 1 (Fastest)
0.54
0.75
0.57
0.55
0.55
0.50
0.50
0.60
0.55
0.25
0.20
Zo = HSTL: ~20Ω
t
R
ispClock
SSTL: 40Ω
0.76
0.69
0.69
0.77
0.40
0.40
0.45
0.45
0.40
0.20
0.20
Zo = 50Ω
t
F
50Ω/3"
0.60
0.88
0.65
0.60
—
—
—
—
—
—
—
t
R
Slew 2
50Ω/3"
50Ω/36"
0.87
0.78
0.78
0.87
—
—
—
—
—
—
—
t
F
1-9
50Ω/36"
0.78
0.83
0.99
0.78
—
—
—
—
—
—
—
t
R
1, 2
50Ω
Slew 3
ispClock5600A Family Data Sheet
1.26
1.11
0.98
1.26
950Ω
—
—
—
—
—
—
—
t
F
SCOPE
50Ω 5pF
Slew 4 (Slowest)
1.05
1.20
1.65
1.05
950Ω
VTERM
t
—
—
—
—
—
—
—
R
SCOPE
50Ω 5pF
1.88
1.68
1.51
1.88
—
—
—
—
—
—
—
t
F
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns