ispPAC-CLK5620AV-01TN100I Lattice, ispPAC-CLK5620AV-01TN100I Datasheet - Page 8

Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I

ispPAC-CLK5620AV-01TN100I

Manufacturer Part Number
ispPAC-CLK5620AV-01TN100I
Description
Clock Drivers & Distribution ISP 0 Dlay Clck Gen w/Unv Fan-Out Buf I
Manufacturer
Lattice

Specifications of ispPAC-CLK5620AV-01TN100I

Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Maximum Operating Temperature
70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-CLK5620AV-01TN100I
Manufacturer:
LATTICE
Quantity:
210
Part Number:
ISPPAC-CLK5620AV-01TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Switching Characteristics – Timing Adders for I/O Modes
t
LVTTL_in
LVCMOS18_in
LVCMOS25_in
LVCMOS33_in
SSTL18_in
SSTL2_in
SSTL3_in
HSTL_in
eHSTL_in
LVDS_in
LVPECL_in
t
LVTTL_out
LVCMOS18_out
LVCMOS25_out
LVCMOS33_out
SSTL2_out
SSTL3_out
SSTL18_out_diff
HSTL_out_diff
eHSTL_out_diff
SSTL_out_diff
LVDS_out
LVPECL_out
t
Slew_1
Slew_2
Slew_3
Slew_4
1. Measured under standard output load conditions. See Figures 1-3-1-5.
2. All input adders referenced to LVCMOS33.
3. All output adders referenced to LVDS.
IOI
IOO
IOS
Input Adders
Output Slew Rate Adders
Output Adders
Adder Type
2
1, 3
Using LVTTL Standard
Using LVCMOS 1.8V Standard
Using LVCMOS 2.5V Standard
Using LVCMOS 3.3V Standard
Using SSTL18 Standard
Using SSTL2 Standard
Using SSTL3 Standard
Using HSTL Standard
Using eHSTL Standard
Using LVDS Standard
Using LVPECL Standard
Output Configured as LVTTL Buffer
Output Configured as LVCMOS 1.8V Buffer
Output Configured as LVCMOS 2.5V Buffer
Output Configured as LVCMOS 3.3V Buffer
Output Configured as SSTL2 Buffer
Output Configured as SSTL3 Buffer
Output Configured as SSTL18 Buffer (Differential)
Output Configured as HSTL Buffer (Differential)
Output Configured as eHSTL Buffer (Differential)
Output Configured as SSTL2 Buffer (Differential)
Output Configured as LVDS Buffer
Output Configured as LVPECL Buffer
Output Slew_1 (Fastest)
Output Slew_2
Output Slew_3
Output Slew_4 (Slowest)
1
Description
1-8
ispClock5600A Family Data Sheet
Min.
-109
-153
-146
-187
231
128
118
201
116
155
124
116
-99
-97
-16
10
64
34
-4
0
0
0
0
1320
Typ.
360
420
380
672
514
426
593
395
510
387
395
180
173
330
660
-17
80
66
78
41
83
0
0
0
0
0
Max.
1064
315
642
679
630
846
651
937
553
730
592
553
209
242
228
402
375
305
57
0
0
0
0
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps

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