LFXP2-5E-5QN208C Lattice, LFXP2-5E-5QN208C Datasheet - Page 33

FPGA - Field Programmable Gate Array 5K LUTs 146I/O Inst- on DSP 1.2V -5 Spd

LFXP2-5E-5QN208C

Manufacturer Part Number
LFXP2-5E-5QN208C
Description
FPGA - Field Programmable Gate Array 5K LUTs 146I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-5E-5QN208C

Number Of Macrocells
5000
Maximum Operating Frequency
200 MHz
Number Of Programmable I/os
146
Data Ram Size
10 KB
Supply Voltage (max)
1.14 V
Supply Current
17 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.26 V
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LFXP2-5E-5QN208C
Manufacturer:
LATTICE
Quantity:
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Part Number:
LFXP2-5E-5QN208C
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Quantity:
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Part Number:
LFXP2-5E-5QN208C
0
Architecture
Lattice Semiconductor
LatticeXP2 Family Data Sheet
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysIO buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-27 shows the Tristate Register Block with the Output Block
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as D-
type or latch. In DDR mode, ONEG1 and OPOS1 are fed into registers on the positive edge of the clock. Then in
the next clock the registered OPOS1 is latched. A multiplexer running off the same clock cycle selects the correct
register for feeding to the output (D0).
Control Logic Block
The control logic block allows the selection and modification of control signals for use in the PIO block. A clock sig-
nal is selected from general purpose routing, ECLK1, ECLK2 or a DQS signal (from the programmable DQS pin)
and is provided to the input register block. The clock can optionally be inverted.
DDR Memory Support
PICs have additional circuitry to allow implementation of high speed source synchronous and DDR memory inter-
faces.
PICs have registered elements that support DDR memory interfaces. Interfaces on the left and right edges are
designed for DDR memories that support 16 bits of data, whereas interfaces on the top and bottom are designed
for memories that support 18 bits of data. One of every 16 PIOs on the left and right and one of every 18 PIOs on
the top and bottom contain delay elements to facilitate the generation of DQS signals. The DQS signals feed the
DQS buses which span the set of 16 or 18 PIOs. Figure 2-28 and Figure 2-29 show the DQS pin assignments in
each set of PIOs.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. For additional information on using DDR memory support please
see TN1138,
LatticeXP2 High Speed I/O
Interface.
2-30

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