LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 128

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.7 (03-15-10)
6.2.1
REGISTER NAME
WORD_SWAP
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
BYTE_TEST
FREE_RUN
PMT_CTRL
GPIO_CFG
GPT_CFG
GPT_CNT
IRQ_CFG
FIFO_INT
HW_CFG
INT_STS
RX_CFG
TX_CFG
ID_REV
INT_EN
Special Restrictions on Back-to-Back Write/Read Cycles
It is important to note that there are specific restrictions on the timing of back-to-back write-read
operations. These restrictions concern reading the control registers after any write cycle to the
LAN9220 device. In many cases there is a required minimum delay between writing to the LAN9220,
and the subsequent side effect (change in the control register value). For example, when writing to the
TX Data FIFO, it takes up to 165ns for the level indication to change in the TX_FIFO_INF register.
In order to prevent the host from reading stale data after a write operation, minimum wait periods must
be enforced. These periods are specified in
processor is required to wait the specified period of time after any write to the LAN9220 before reading
the resource specified in the table. These wait periods are for read operations that immediately follow
any write cycle. Note that the required wait period is dependant upon the register being read after the
write.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to guarantee that the
minimum write-to-read timing restriction is met.
are required before reading the register indicated. The number of BYTE_TEST reads in this table is
based on the minimum timing for Tcycle (165ns). For microprocessors with slower busses the number
of reads may be reduced as long as the total time is equal to, or greater than the time specified in the
table. Note that dummy reads of the BYTE_TEST register are not required as long as the minimum
time period is met.
Table 6.1 Read After Write Timing Rules
FOLLOWING ANY WRITE CYCLE
MINIMUM WAIT TIME FOR READ
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
DATASHEET
(IN NS)
165
165
165
165
165
165
165
165
165
330
165
165
165
165
330
0
0
0
128
Table 6.1, "Read After Write Timing
Table 6.1
also shows the number of dummy reads that
(ASSUMING T
NUMBER OF BYTE_TEST
READS
CYCLE
0
1
1
1
0
1
1
1
1
1
0
1
2
1
1
1
1
2
Rules". The host
OF 165NS)
SMSC LAN9220
Datasheet