LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 43
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LAN9220-ABZJ
Manufacturer Part Number
LAN9220-ABZJ
Description
Ethernet ICs 16Bit Single Chip Ethernet Controller
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet
1.LAN9220-ABZJ.pdf
(151 pages)
Specifications of LAN9220-ABZJ
Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
85 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN9220-ABZJ
Manufacturer:
RENESAS
Quantity:
101
Part Number:
LAN9220-ABZJ
Manufacturer:
SMSC
Quantity:
20 000
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
3.9.2.2
3.9.2.3
3.9.2.4
3.10
3.10.1
3.10.2
Table 3.9, "Required EECLK
each EEPROM operation.
MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register.
If a value of 0xA5h is not found in the first address of the EEPROM, the EEPROM is assumed to be
un-programmed and MAC Address Reload operation will fail. The “MAC Address Loaded” bit indicates
a successful load of the MAC address. The EPC_LOAD bit is set after a successful reload of the MAC
address.
EEPROM Command and Data Registers
Refer to
"E2P_DATA – EEPROM Data Register," on page 104
Supported EEPROM operations are described in these sections.
EEPROM Timing
Refer to
The LAN9220 supports power-down modes to allow applications to minimize power consumption. The
following sections describe these modes.
System Description
Power is reduced to various modules by disabling the clocks as outlined in Table 3.10, “Power
Management States,” on page 45. All configuration data is saved when in either of the two low power
states. Register contents are not affected unless specifically indicated in the register description.
Functional Description
There is one normal operating power state, D0 and there are two power saving states: D1, and D2.
Upon entry into either of the two power saving states, only the PMT_CTRL register is accessible for
read operations. In either of the power saving states the READY bit in the PMT_CTRL register will be
cleared. Reads of any other addresses are forbidden until the READY bit is set. All writes, with the
exception of the wakeup write to BYTE_TEST, are also forbidden until the READY bit is set. Only when
in the D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed.
Power Management
OPERATION
ERASE
WRITE
EWDS
EWEN
WRAL
READ
ERAL
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 102
Section 6.11, "EEPROM Timing," on page 138
Table 3.9 Required EECLK Cycles
Cycles", shown below, shows the number of EECLK cycles required for
DATASHEET
43
REQUIRED EECLK CYCLES
for detailed EEPROM timing specifications.
for a detailed description of these registers.
10
10
10
10
18
18
18
and
Revision 2.7 (03-15-10)
Section 5.3.24,