LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 133

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
6.6
SYMBOL
t
t
t
t
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
ah
In this mode the upper address inputs are not decoded, and any burst read of the LAN9220 will read
the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This
is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode
is useful when the host processor must increment its address when accessing the LAN9220. Timing
is identical to a PIO Burst Read, and the FIFO_SEL signal has the same timing characteristics as the
address lines.
In this mode, performance is improved by allowing an unlimited number of back-to-back read cycles.
RX Data FIFO Direct PIO Burst Reads can be performed using Chip Select (nCS) or Read Enable
(nRD). When either or both of these control signals go high, they must remain high for the period
specified.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits.
Note 6.5
Note: An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted.
RX Data FIFO Direct PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address, FIFO_SEL Setup to nCS, nRD Valid
Address Stable to Data Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and
deasserted in any order.
Figure 6.5 RX Data FIFO Direct PIO Burst Read Cycle Timing
When VDDVARIO is 3.3V or 2.5V, the maximum T
1.8V, the maximum T
Table 6.6 RX Data FIFO Direct PIO Burst Read Cycle Timing
doff
DATASHEET
time is 9ns.
133
MIN
165
13
0
0
0
0
doff
time is 7ns. When VDDVARIO is
TYP
Note 6.5
MAX
Revision 2.7 (03-15-10)
30
40
UNITS
ns
ns
ns
ns
ns
ns
ns