LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 97

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
5.3.16
5.3.17
31-16
BITS
BITS
15-0
31:0
Reserved
General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
Word Swap. If this field is set to 00000000h, or anything except
0xFFFFFFFFh, the LAN9220 maps words with address bit A[1]=1 to the
high order words of the CSRs and Data FIFOs, and words with address bit
A[1]=0 to the low order words of the CSRs and Data FIFOs. If this field is
set to 0xFFFFFFFFh, the LAN9220 maps words with address bit A[1]=1 to
the low order words of the CSRs and Data FIFOs, and words with address
bit A[1]=0 to the high order words of the CSRs and Data FIFOs.
Note:
GPT_CNT-General Purpose Timer Current Count Register
This register reflects the current value of the GP Timer.
WORD_SWAP—Word Swap Control
This register controls how words from the host data bus are mapped to the CSRs and Data FIFOs
inside the LAN9220. The LAN9220 always sends data from the Transmit Data FIFO to the network so
that the low order word is sent first, and always receives data from the network to the Receive Data
FIFO so that the low order word is received first.
Offset:
Offset:
Word swap is used in conjunction with the mixed endian
functionality to determine the final byte ordering. Refer to
3.7.3, "Mixed Endian Support"
DESCRIPTION
DESCRIPTION
90h
98h
DATASHEET
for more information.
97
Size:
Size:
Section
32 bits
32 bits
NASR
TYPE
TYPE
R/W
RO
RO
Revision 2.7 (03-15-10)
00000000h
DEFAULT
DEFAULT
FFFFh
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