LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 31

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
1DWORD
1DWORD
DST
0
The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN
protocol identifier for the third tag is treated as an Ethernet type field. The checksum calculation will
begin immediately after the type field.
The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it
calculates the 16-bit checksum. The RXCOE passes the Ethernet frame to the RX Data FIFO with the
checksum appended to the end of the frame. The RXCOE inserts the checksum immediately after the
last byte of the Ethernet frame. The packet length field in the RX status word (refer to
will indicate that the frame size has increased by two bytes to accommodate the checksum.
Setting the RXCOE_EN bit in the
RXCOE, while the RXCOE_MODE bit selects the operating mode. When the RXCOE is disabled, the
the received data is simply passed through the RXCOE unmodified.
Note: Software applications must stop the receiver and flush the RX data path before changing the
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of
DST
0
1
SRC
Figure 3.9 Ethernet Frame with multiple VLAN Tags and SNAP Header
1
{DSAP, SSAP, CTRL,
state of the RXCOE_EN or RXCOE_MODE bits.
the
simultaneously.
SRC
2
{DSAP, SSAP, CTRL,
2
OUI[23:16]}
Figure 3.8 Ethernet Frame with VLAN Tag and SNAP Header
MAC_CR—MAC Control
8
1
0
0
4
OUI[23:16]}
8
1
0
0
V
I
D
3
V
I
D
8
1
0
0
5
L
e
n
V
I
D
4
L
e
n
S
N
A
P
0
6
S
N
A
P
0
5
S
N
A
P
1
7
S
N
A
P
1
6
8
COE_CR—Checksum Offload Engine Control Register
{OUI[15:0], PID[15:0]}
DATASHEET
Register) and vice versa. These functions cannot be enabled
{OUI[15:0], PID[15:0]}
31
Calculate Checksum
Calculate Checksum
L3 Packet
L3 Packet
Revision 2.7 (03-15-10)
C
F
S
Section
F
C
S
enables the
3.13.3)