LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 79

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
5.3
BASE ADDRESS
+ OFFSET
B8h - FCh
ACh
5Ch
6Ch
7Ch
8Ch
9Ch
50h
54h
58h
60h
64h
68h
70h
74h
78h
80h
84h
88h
90h
94h
98h
A0h
A4h
A8h
B0h
B4h
Table 5.1, "Direct Address Register
bus.
System Control and Status Registers
MAC_CSR_DATA
MAC_CSR_CMD
WORD_SWAP
RX_FIFO_INF
TX_FIFO_INF
RX_DP_CTL
BYTE_TEST
RESERVED
RESERVED
RESERVED
FREE_RUN
PMT_CTRL
GPIO_CFG
E2P_DATA
RX_DROP
GPT_CFG
E2P_CMD
GPT_CNT
AFC_CFG
IRQ_CFG
FIFO_INT
HW_CFG
SYMBOL
INT_STS
RX_CFG
TX_CFG
ID_REV
INT_EN
Table 5.1 Direct Address Register Map
CONTROL AND STATUS REGISTERS
Map", lists the registers that are directly addressable by the host
DATASHEET
Chip ID and Revision.
Main Interrupt Configuration
Interrupt Status
Interrupt Enable Register
Reserved for future use
Read-only byte order testing register
FIFO Level Interrupts
Receive Configuration
Transmit Configuration
Hardware Configuration
RX Datapath Control
Receive FIFO Information
Transmit FIFO Information
Power Management Control
General Purpose IO Configuration
General Purpose Timer Configuration
General Purpose Timer Count
Reserved for future use
WORD SWAP Register
Free Run Counter
RX Dropped Frames Counter
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
MAC CSR Synchronizer Data
Automatic Flow Control Configuration
EEPROM Command
EEPROM Data
Reserved for future use
79
REGISTER NAME
Revision 2.7 (03-15-10)
See Page 80.
0000FFFFh
0000FFFFh
00000000h
00000000h
00000000h
87654321h
48000000h
00000000h
00000000h
00050000h
00000000h
00000000h
00001200h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
DEFAULT
-
-
-
-