LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 18

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LAN9220-ABZJ

Manufacturer Part Number
LAN9220-ABZJ
Description
Ethernet ICs 16Bit Single Chip Ethernet Controller
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet

Specifications of LAN9220-ABZJ

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
85 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Revision 2.7 (03-15-10)
Auto-MDIX Enable
Crystal 1, Clock In
Wakeup Indicator
Crystal 2
NAME
Reset
XTAL1/CLKIN
AMDIX_EN
SYMBOL
nRESET
XTAL2
PME
Table 2.4 System and Power Signals
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
BUFFER
OCLK
VOD8
TYPE
lCLK
(PU)
(PU)
VO8/
VIS
VIS
DATASHEET
18
PINS
NUM
1
1
1
1
1
External 25MHz Crystal Input. This pin can also
be connected to single-ended TTL oscillator
(CLKIN). If this method is implemented, XTAL2
should be left unconnected.
External 25MHz Crystal output.
Active-low reset input. Resets all logic and
registers within the LAN9220. This signal is
pulled high with a weak internal pull-up resistor.
Note:
Note:
When programmed to do so, is asserted when
the LAN9220 detects a wake event and is
requesting the system to wake up from the
associated sleep state. The polarity and buffer
type of this signal is programmable.
Note:
Enables Auto-MDIX. Pull high or leave
unconnected to enable Auto-MDIX, pull low to
disable Auto-MDIX.
Note:
The LAN9220 must be reset on
power-up via nRESET or following
power-up via a soft reset (SRST). The
LAN9220 must always be read at least
once after reset, or upon return from a
power-saving state or write operations
will not function. See
"Detailed Reset Description," on
page 47
When operating at reduced
VDDVARIO voltage levels (less than
3.0V), this pin must be pulled-high to
a valid level with an external resistor
or must be driven as an input. Refer to
Section 2.2, "External Pull-Up/Pull-
Down Resistors"
Detection of a Power Management
Event, and assertion of the PME
signal will not wakeup the LAN9220.
The LAN9220will only wake up when it
detects a host write cycle (assertion of
nCS and nWR). Although any write to
the LAN9220, regardless of the data
written, will wake-up the device when
it is in a power-saving mode, it is
required that the BYTE_TEST register
be used for this purpose.
When operating at reduced
VDDVARIO voltage levels (less than
3.0V), this pin must be pulled to a valid
level with an external resistor. Refer to
Section 2.2, "External Pull-Up/Pull-
Down Resistors"
DESCRIPTION
for additional information
for more information.
for more information.
Section 3.11,
SMSC LAN9220
Datasheet

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