LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 131

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LAN9220-ABZJ

Manufacturer Part Number
LAN9220-ABZJ
Description
Ethernet ICs 16Bit Single Chip Ethernet Controller
Manufacturer
SMSC
Type
Single Chip MAC and PHY Controllerr
Datasheet

Specifications of LAN9220-ABZJ

Ethernet Connection Type
10 Base-T, 100 Base-TX
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Product
Ethernet Controllers
Number Of Transceivers
1
Standard Supported
802.3, 802.3u
Data Rate
10 MB, 100 MB
Supply Voltage (max)
3.3 V
Supply Voltage (min)
0 V
Supply Current (max)
85 mA
Maximum Operating Temperature
+ 70 C
Package / Case
TQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
6.4
SYMBOL
nCS, nRD
t
t
t
t
t
t
t
t
csdv
acyc
t
csh
asu
adv
don
doff
doh
A[7:5]
A[4:1]
Data Bus
ah
In this mode, performance is improved by allowing up to 16 WORD read cycles back-to-back. PIO
Burst Reads can be performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these
control signals must go high between bursts for the period specified.
Note: The “Data Bus” width is 16 bits
Note 6.3
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when
PIO Burst Reads
DESCRIPTION
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
When VDDVARIO is 3.3V or 2.5V, the maximum T
1.8V, the maximum T
Figure 6.3 PIO Burst Read Cycle Timing
Table 6.4 PIO Burst Read Timing
doff
DATASHEET
time is 9ns.
131
MIN
165
13
0
0
0
0
doff
time is 7ns. When VDDVARIO is
TYP
Note 6.3
MAX
Revision 2.7 (03-15-10)
30
40
UNITS
ns
ns
ns
ns
ns
ns
ns

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