LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 135

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
6.8
SYMBOL
FIFO_SEL
nCS, nWR
Data Bus
t
cycle
t
t
t
t
t
t
csh
asu
dsu
A[2:1]
csl
ah
dh
In this mode the upper address inputs are not decoded, and any write to the LAN9220 will write the
TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is
normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9220. Timing is
identical to a PIO write, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note: The “Data Bus” width is 16 bits.
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The
TX Data FIFO Direct PIO Writes
DESCRIPTION
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time (see Note below)
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
cycle ends when either or both nCS and nWR are deasserted. They may be asserted and
deasserted in any order. Parameters t
the t
cycle
minimum.
Figure 6.7 TX Data FIFO Direct PIO Write Timing
Table 6.8 TX Data FIFO Direct PIO Write Timing
DATASHEET
135
csh
and t
csl
must be extended using wait states to meet
MIN
165
32
13
0
7
0
0
TYP
133
MAX
Revision 2.7 (03-15-10)
UNITS
ns
ns
ns
ns
ns
ns
ns