LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 13

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
Datasheet
SMSC LAN9220
1.5
1.6
1.7
1.8
1.9
1.10
can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working
buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX
FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode
and will queue an entire frame before beginning transmission.
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a
conduit between the host interface and the MAC through which all transmitted and received data and
status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the
various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the
MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are
configurable in size, allowing increased flexibility.
The LAN9220 supports a single programmable interrupt. The programmable nature of this interrupt
allows the user the ability to optimize performance dependent upon the application requirement. Both
the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing.
The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with
other devices. In addition, a programmable interrupt de-assertion interval is provided.
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the
LAN9220. It is accessible through the host bus interface via the CSRs. The GPIO signals can function
as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also
be configured to trigger interrupts with programmable polarity.
A serial EEPROM interface is included in the LAN9220. The serial EEPROM is optional and can be
programmed with the LAN9220 MAC address. The LAN9220 can optionally load the MAC address
automatically after hardware reset, or soft reset.
The LAN9220 supports comprehensive array of power management modes to allow use in power
sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported
by the LAN9220. An external PME (Power Management Event) interrupt is provided to indicate
detection of a wakeup event.
The general-purpose timer has no dedicated function within the LAN9220 and may be programmed to
issue a timed interrupt.
Receive and Transmit FIFOs
Interrupt Controller
GPIO Interface
Serial EEPROM Interface
Power Management Controls
General Purpose Timer
DATASHEET
13
Revision 2.7 (03-15-10)