LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 34

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.7 (03-15-10)
3.7.3
3.7.4
Mixed Endian Support
In order to allow flexibility with a range of designs, theLAN9220 supports mixed endian Data FIFO
accesses. The LAN9220 provides the ability to select Data FIFO endianess separately for accesses
through the Data FIFO ports (addresses 00h-3Ch) or using the FIFO_SEL input signal. This is
accomplished via the FPORTEND and FSELEND bits of the
Register, respectively.
The FPORTEND bit determines the endianess of RX and TX Data FIFO host accesses made through
the Data FIFO port addresses (00h-3Ch). When FPORTEND is cleared, Data FIFO port accesses
utilize little endian byte ordering. When FPORTEND is set, Data FIFO port accesses utilize big endian
byte ordering.
The FSELEND bit determines the endianess of RX and TX Data FIFO host accesses when using the
FIFO_SEL signal. When FSELEND is cleared, FIFO_SEL accesses utilize little endian byte ordering.
When FSELEND is set, FIFO_SEL accesses utilize big endian byte ordering.
In addition to mixed endian support, the LAN9220 provides a word swap function, as described in
Section
determines how the Data/Status FIFO’s and CSR host access byte ordering is applied.
describes the various operation modes of the endianess and word swap ordering logic.
illustrates the FIFO access byte ordering under various endianess and word swap settings. Refer to
Section 3.7.4
Note: CSR and status FIFO accesses are not affected by the FPORTEND and FSELEND endianess
Word Swap Function
In addition to mixed endian functionality, the LAN9220 supports a Word Swap Function. This feature
is controlled by the Word Swap Register, which is described in
Swap Control," on page
the Control and Status Registers and the Transmit and Receive Data/Status FIFOs.
Both the word swap function and the mixed endian control bits contain the ability to change the byte
ordering of host data path accesses.
endianess select logic is applied within the LAN9220. Logically, the endian control logic is applied after
the word swap logic for write operations, and before the word swap logic for read operations.
select bits.
3.7.4. The word swap function combined with the endianess select bits described above
for additional details.
97. This register affects how words on the data bus are written to or read from
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
DATASHEET
Figure 3.2
34
illustrates the order in which the word swap and
Section 5.3.17, "WORD_SWAP—Word
HW_CFG—Hardware Configuration
SMSC LAN9220
Figure 3.3
Datasheet
Table 3.8