LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 44

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.7 (03-15-10)
3.10.2.1
3.10.2.2
Note 3.10 The LAN9220 must always be read at least once after power-up, reset, or upon return from
In system configurations where the PME signal is shared amongst multiple devices, the WUPS field
within the PMT_CTRL register can be read to determine which LAN9220 device is driving the PME
signal.
When the LAN9220 is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST register
will return the LAN9220 to the D0 state.
Components,” on page 141
page
Note 3.11 When the LAN9220 is in a power saving state, a write of any data to the BYTE_TEST
D1 Sleep
Power consumption is reduced in this state by disabling clocks to portions of the internal logic as
shown in
operational. This state is entered when the host writes a '01' to the PM_MODE bits in the Power
Management (PMT_CTRL) register. The READY bit in PMT_CTRL is cleared when entering the D1
state.
Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly
enabled via the WOL_EN and PME_EN bits, the LAN9220 will assert the PME hardware signal upon
the detection of the wake-up frame or magic packet. The LAN9220 can also assert the host interrupt
(IRQ) on detection of a wake-up frame or magic packet. Upon detection, the WUPS field in PMT_CTRL
will be set to a 10b.
Note 3.12 The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the
Note 3.13 Wake-up frame and Magic Packet detection is automatically enabled when entering the D1
A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was
detected, will return LAN9220 to the D0 state and will reset the PM_MODE field to the D0 state. As
noted above, the host is required to check the READY bit and verify that it is set before attempting
any other reads or writes of the device.
Note 3.14 The host must only perform read accesses prior to the ready bit being set.
Once the READY bit is set, the LAN9220 is ready to resume normal operation. At this time the WUPS
field can be cleared.
D2 Sleep
In this state, as shown in
placed in a reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY
(Mode Control/Status register) must be set. This places the PHY in the Energy Detect mode. The
PM_MODE bits in the PMT_CTRL register must then be set to 10b. Upon setting the PM_MODE bits,
the LAN9220 will enter the D2 sleep state. The READY bit in PMT_CTRL is cleared when entering the
D2 state.
Note 3.15 If carrier is present when this state is entered detection will occur immediately.
If properly enabled via the ED_EN and PME_EN bits, the LAN9220 will assert the PME hardware
signal upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to
a 01b.
141, shows the power consumption values for each power state.
Table
a power-saving state, otherwise write operations will not function.
register will wake-up the device. DO NOT PERFORM WRITES TO OTHER
ADDRRESSES while the READY bit in the PMT_CTRL register is cleared.
setting of PME_EN.
state. For wake-up frame detection, the wake-up frame filter must be programmed before
entering the D1 state (see
the host interrupt and PME signal must be enabled prior to entering the D1 state.
3.10. In this mode the clock to the internal PHY and portions of the MAC are still
Table
and
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
3.10, all clocks to the MAC and host bus are disabled and the PHY is
Table 7.2, “Power Consumption Device and System Components,” on
DATASHEET
Section 3.5, "Wake-up Frame Detection," on page
44
Table 7.2, “Power Consumption Device and System
SMSC LAN9220
26). If used,
Datasheet