LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 66

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.7 (03-15-10)
3.13.4
3.13.5
BITS
7
6
5
4
3
2
1
0
Frame Too Long. When set, this bit indicates that the frame length exceeds the maximum Ethernet
specification of 1518 bytes. This is only a frame too long indication and will not cause the frame
reception to be truncated.
Collision Seen. When set, this bit indicates that the frame has seen a collision after the collision
window. This indicates that a late collision has occurred.
Frame Type. When set, this bit indicates that the frame is an Ethernet-type frame (Length/Type field
in the frame is greater than 1500). When reset, it indicates the incoming frame was an 802.3 type
frame. This bit is not set for Runt frames less than 14 bytes.
Receive Watchdog time-out. When set, this bit indicates that the incoming frame is greater than
2048 bytes through 2560 bytes, therefore expiring the Receive Watchdog Timer.
MII Error. When set, this bit indicates that a receive error (RX_ER asserted) was detected during
frame reception.
Dribbling Bit. When set, this bit indicates that the frame contained a non-integer multiple of 8 bits.
This error is reported only if the number of dribbling bits in the last byte is 4 in the MII operating mode,
or at least 3 in the 10 Mbps operating mode. This bit will not be set when the collision seen bit[6] is
set. If set and the CRC error bit[1] is cleared, then the packet is considered to be valid.
CRC Error. When set, this bit indicates that a CRC error was detected. This bit is also set when the
RX_ER pin is asserted during the reception of a frame even though the CRC may be correct. This bit
is not valid if the received frame is a Runt frame, or a late collision was detected or when the
Watchdog Time-out occurs.
Reserved. These bits are reserved. Reads 0
Stopping and Starting the Receiver
To stop the receiver, the host must clear the RXEN bit in the MAC Control Register. When the receiver
is halted, the RXSTOP_INT will be pulsed. Once stopped, the host can optionally clear the RX status
and RX data FIFOs. The host must re-enable the receiver by setting the RXEN bit.
Receiver Errors
If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX
Error (RXE) will be asserted under the following conditions:
It is the duty of the host to identify and resolve any error conditions.
A host underrun of RX data FIFO
A host underrun of the RX status FIFO
An overrun of the RX status FIFO
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
DATASHEET
DESCRIPTION
66
SMSC LAN9220
Datasheet