LAN9220-ABZJ SMSC, LAN9220-ABZJ Datasheet - Page 94

• Manufacturer Part Number: LAN9220-ABZJ
• Description: Ethernet ICs 16Bit Single Chip Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9220-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 85 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 2.7 (03-15-10)
BITS
5-4
3
2
1
0
WAKE-UP Status (WUPS) – This field indicates the cause of a wake-up
event detection as follows
00b -- No wake-up event detected
01b -- Energy detected
10b -- Wake-up frame or magic packet detected
11b -- Indicates multiple events occurred
WUPS bits are cleared by writing a ‘1’ to the appropriate bit. The device must
return to the D0 state (READY bit set) before these bits can be cleared.
Note:
PME indication (PME_IND). The PME signal can be configured as a pulsed
output or a static signal, which is asserted upon detection of a wake-up
event.
When set, the PME signal will pulse active for 50mS upon detection of a
wake-up event.
When clear, the PME signal is driven continuously upon detection of a wake-
up event.
The PME signal can be deactivated by clearing the WUPS bits, or by
clearing the appropriate enable (refer to
Management Event Indicators," on page
PME Polarity (PME_POL). This bit controls the polarity of the PME signal.
When set, the PME output is an active high signal. When reset, it is active
low. When PME is configured as an open-drain output this field is ignored,
and the output is always active low.
PME Enable (PME_EN). When set, this bit enables the external PME signal.
This bit does not affect the PME interrupt (PME_INT).
Device Ready (READY). When set, this bit indicates that LAN9220 is ready
to be accessed. This register can be read when LAN9220 is in any power
management mode. Upon waking from any power management mode,
including power-up, the host processor can interrogate this field as an
indication when LAN9220 has stabilized and is fully alive. Reads and writes
of any other address are invalid until this bit is set.
Note:
Note:
In order to clear this bit, it is required that all event sources be
cleared as well. The event sources are described in
PME and PME_INT Signal Generationon page
With the exception of HW_CFG and PMT_CTRL, read access to
any internal resources is forbidden while the READY bit is cleared.
On power-up, this bit can be polled to indicate when a valid soft
reset (SRST) can be performed.
16-bit Non-PCI Small Form Factor 10/100 Ethernet Controller with Variable Voltage I/O & HP Auto-MDIX Support
DESCRIPTION
DATASHEET
Section 3.10.2.3, "Power
46).
94
46.
Figure 3.12
NASR
R/WC
TYPE
R/W
R/W
R/W
RO
SMSC LAN9220
DEFAULT
Datasheet
00
0b
0b
0b
-