XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 125

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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DS083 (v4.7) November 5, 2007
Product Specification
08/25/03
09/10/03
10/14/03
11/10/03
12/05/03
Date
R
Version
2.10
2.11
2.12
2.9
3.0
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Updated time and frequency parameters as per speedsfile v1.81.
Table
Table
Table 50
specified a capacitive load parameter.
Table
erroneously omitted from the full data sheet file (all four modules concatenated),
though not from the stand-alone Module 3 file. The omitted parameters have been
restored.
Table 61
labeled. Previously expressed in nanoseconds, but labeled picoseconds.
Figure 6: Added note to figure regarding termination resistors.
Table
temperature” to “Maximum junction temperature”. Added new Footnote (2) linking to
website for package thermal data.
Table 4
outputs (SSO).
In section
-
-
-
-
Table
Footnote (2) to new Footnote (3).
Table
Table
XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
-5 and -6, updated and released to Production status as per speedsfile v1.83.
Figure
must be held to a constant DC level during and after configuration.
Table
constant DC level during and after configuration.
Table
or more banks operated at 3.3V. Changed T
devices through XC2VP70. Added Industrial Grade multiplier specification to Footnote
(1) in both tables.
In section
11713 with reference to
footnote referring to
Featured changes:
-
-
-
-
Table 36
Added new
Replaced
Revised and extended text describing output delay measurement procedure.
Speedsfile parameter values for -7 speed grade added for devices
XC2VP2-XC2VP70.
Table 13
values added.
Table
All remaining source-synchronous parameter values added
1: Footnote (2) rewritten to specify “one or more banks.”
2: Added footnote referring to XAPP659 for 3.3V I/O operation.
54: Due to a document compilation error in v2.8, some DCM parameters were
5: Added I
46: Added footnote indicating that mode pins M0, M1, and M2 must be held to a
1: Deleted Footnote (2), which had derated the absolute maximum T
55: For Input Clock Low/High Pulse Width, PSCLK and CLKIN, changed existing
1: Changed 3.3V absolute max V
4: Removed MIN column from table.
7: Changed representation of mode pins M0, M1, and M2 indicating that they
and
and
and
61: New parameter T
General Power Supply
I/O Standard Adjustment Measurement
Table
renamed
and
Table
Table
Figure
Table
CCINTMIN
Table
www.xilinx.com
5: Filled in power-on and quiescent current parameters for all
51: Revised test setup footnote to refer to
63: Corrected parameters to expression in picoseconds, as
XAPP659
6,
37,
Input Delay Measurement
14: Pin-to-pin and register-to_register performance parameter
Generalized Test
XAPP689
Output Delay Measurement
for XC2VP30 device.
.
DCD_LOCAL
Requirements, replaced reference to Answer Record
regarding handling of simultaneously switching
Revision
IN
Setup, with new drawing.
and V
(and footnote) replaces T
J
description from “Operating junction
TS
Methodology. Added footnotes.
Methodology:
from 3.75V to 4.05V. Added
Methodology.
Figure
(Table 61
DCD_CLK0
6. Previously
& following).
J
Module 3 of 4
when one
.
54

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