XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 15

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Output Swing and Emphasis
The output swing and emphasis levels are fully programma-
ble. Each is controlled via attributes at configuration, and
can be modified via the PMA attribute programming bus.
The programmable output swing control can adjust the dif-
ferential peak-to-peak output level between 200 mV and
1600 mV.
With emphasis, the differential voltage swing is boosted to
create a stronger rising or falling waveform. This method
compensates for high frequency loss in the transmission
media that would otherwise limit the magnitude of this wave-
form. Lossy transmission lines cause the dissipation of elec-
trical energy. This emphasis technique extends the distance
that signals can be driven down lossy line media and
increases the signal-to-noise ratio at the receiver.
Emphasis can be described from two perspectives, additive
to the smaller voltage (V
from the larger voltage (V
benefits in compensating for channel loss are identical. It is
simply a relative way of specifying the effect at the transmit-
ter.
The equations for calculating pre-emphasis as a percent-
age and dB are as follows:
The equations for calculating de-emphasis as a percentage
and dB are as follows:
The pre-emphasis amount can be programmed in discrete
steps between 0% and 500%. The de-emphasis amount
can be programmed in discrete steps between 0% and
83%.
Serializer
The serializer multiplies the reference frequency provided
on REFCLK by 10, 16, 20, 32, or 40, depending on the oper-
ation mode. The multiplication of the clock is achieved by
using an embedded PLL.
Data is converted from parallel to serial format and transmit-
ted on the TXP and TXN differential outputs. The electrical
connection of TXP and TXN can be interchanged through
configuration. This option can be controlled by an input
(TXPOLARITY) at the FPGA transmitter interface.
Deserializer
Synchronous serial data reception is facilitated by a clock
and data recovery (CDR) circuit. This circuit uses a fully
monolithic Phase Lock Loop (PLL), which does not require
any external components. The CDR circuit extracts both
phase and frequency from the incoming data stream.
The derived clock, RXRECCLK, is generated and locked to
as long as it remains within the specified component range.
DS083 (v4.7) November 5, 2007
Product Specification
Pre-Emphasis
Pre-Emphasis
De-Emphasis
De-Emphasis
R
%
dB
%
dB
= (V
= 20 log(V
= ((V
= 20 log(V
LG
LG
SM
- V
LG
-V
) (pre-emphasis) or subtractive
) (de-emphasis). The resulting
SM
SM
SM
) / V
) / V
LG
/V
/V
LG
SM
)
SM
LG
)
) x 100
) x 100
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
www.xilinx.com
This clock is presented to the FPGA fabric at
1
ating mode.
A sufficient number of transitions must be present in the
data stream for CDR to work properly. The CDR circuit is
guaranteed to work with 8B/10B and 64B/66B encoding.
Further, CDR requires approximately 5,000 transitions upon
power-up to guarantee locking to the incoming data rate.
Once lock is achieved, up to 75 missing transitions can be
tolerated before lock to the incoming data stream is lost.
Another feature of CDR is its ability to accept an external
precision reference clock, REFCLK, which either acts to
clock incoming data or to assist in synchronizing the derived
RXRECCLK.
For further clarity, the TXUSRCLK is used to clock data from
the FPGA fabric to the TX FIFO. The FIFO depth accounts
for the slight phase difference between these two clocks. If
the clocks are locked in frequency, then the FIFO acts much
like a pass-through buffer.
The receiver can be configured to reverse the RXP and
RXN inputs. This can be useful in the event that printed cir-
cuit board traces have been reversed.
Receiver Lock Control
The CDR circuits will lock to the reference clock automati-
cally if the data is not present. For proper operation, the fre-
quency of the reference clock must be within
the nominal frequency.
During normal operation, the receiver PLL automatically
locks to incoming data (when present) or to the local refer-
ence clock (when data is not present). This is the default
configuration for all primitives. This function can be overrid-
den via the PMARXLOCKSEL port
When receive PLL lock is forced to the local reference,
phase information from the incoming data stream is
ignored. Data continues to be sampled, but synchronous to
the local reference rather than relative to edges in the data
stream.
Receive Equalization
In addition to transmit emphasis, the RocketIO X MGT pro-
vides a programmable active receive equalization feature to
further compensate the effects of channel attenuation at
high frequencies.
By adjusting RXFER, the right amount of equalization can
be added to reverse the signal degradation caused by a
printed circuit board, a backplane, or a line/switch card.
RXFER can be set through software configuration or the
PMA Attribute Bus.
Receiver Termination
On-chip termination is provided at the receiver, eliminating
the need for external termination. The receiver termination
supply (V
/
32
, or
1
/
40
TRX
the incoming data rate depending on the oper-
) is the center tap of differential termination to
1
±
/
10
Module 2 of 4
100 ppm of
,
1
/
16
,
1
/
20
4
,

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