XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 23
Manufacturer Part Number
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Specifications of XC2VP7-5FF672C
Device Logic Units
Number Of Registers
Maximum Internal Frequency
Typical Operating Supply Voltage
Maximum Number Of User I/os
The serializer multiplies the reference frequency provided
on REFCLK by 20. The multiplication of the clock is
achieved by using an embedded PLL.
Data is converted from parallel to serial format and transmit-
ted on the TXP and TXN differential outputs. The electrical
connection of TXP and TXN can be interchanged through
configuration. This option can be controlled by an input
(TXPOLARITY) at the FPGA transmitter interface.
The serial transceiver input is locked to the input data
stream through Clock and Data Recovery (CDR), a built-in
feature of the RocketIO transceiver. CDR keys off the rising
and falling edges of incoming data and derives a clock that
is representative of the incoming data rate.
The derived clock, RXRECCLK, is generated and locked to
as long as it remains within the specified component range.
This clock is presented to the FPGA fabric at
ing data rate.
A sufficient number of transitions must be present in the
data stream for CDR to work properly. CDR requires
approximately 5,000 transitions upon power-up to guaran-
Fabric Data Interface
Internally, the PCS operates in 2-byte mode (16/20 bits).
The FPGA fabric interface can either be 1, 2, or 4 bytes
wide. When accompanied by the predefined modes of the
PMA, the user thus has a large combination of protocols
and data rates from which to choose.
USRCLK2 clocks data on the fabric side, while USRCLK
clocks data on the PCS side. This creates distinct USR-
CLK/USRCLK2 frequency ratios for different combinations
DS083 (v4.7) November 5, 2007
Figure 11: RocketIO Receive Termination
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
tee locking to the incoming data rate. Once lock is achieved,
up to 75 missing transitions can be tolerated before lock to
the incoming data stream is lost. The CDR circuit is guaran-
teed to work with 8B/10B encoding.
Another feature of CDR is its ability to accept an external
precision reference clock, REFCLK, which either acts to
clock incoming data or to assist in synchronizing the derived
For further clarity, the TXUSRCLK is used to clock data from
the FPGA fabric to the TX FIFO. The FIFO depth accounts
for the slight phase difference between these two clocks. If
the clocks are locked in frequency, then the FIFO acts much
like a pass-through buffer.
The receiver can be configured to reverse the RXP and
RXN inputs. This can be useful in the event that printed cir-
cuit board traces have been reversed.
On-chip termination is provided at the receiver, eliminating
the need for external termination. The receiver includes pro-
grammable on-chip termination circuitry for 50Ω (default) or
75Ω impedance, as shown in
of fabric and internal data widths.
USRCLK2 to USRCLK ratios for the three fabric data
No fixed phase relationship is assumed between REFCLK,
RXRECCLK, and/or any other clock that is not tied to either
of these clocks. When RXUSRCLK and RXUSRCLK2 have
different frequencies, each edge of the slower clock is
aligned to a falling edge of the faster clock. The same rela-
tionships apply to TXUSRCLK and TXUSRCLK2.
Module 2 of 4