XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 55

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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CLB/Slice Configurations
Table 19
implemented in one of the configurations listed.
Table 19: Logic Resources in One CLB
Table 20: Virtex-II Pro Logic Resources Available in All CLBs
18 Kb Block SelectRAM+ Resources
Introduction
Virtex-II Pro devices incorporate large amounts of 18 Kb
block SelectRAM+ resources. These complement the dis-
tributed SelectRAM+ resources that provide shallow RAM
structures implemented in CLBs. Each Virtex-II Pro block
SelectRAM+ resource is an 18 Kb true dual-port RAM with
two independently clocked and independently controlled
synchronous ports that access a common storage area.
Both ports are functionally identical. CLK, EN, WE, and
SSR polarities are defined through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM+ behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
DS083 (v4.7) November 5, 2007
Product Specification
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VPX20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
Slices
Device
4
summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or slice can be
R
LUTs
CLB Array:
8
104 x 82
Column
104 x 82
120 x 94
16 x 22
40 x 22
40 x 34
56 x 46
56 x 46
80 x 46
88 x 58
88 x 70
Row x
Flip-Flops
8
Number
33,088
13,696
19,392
23,616
33,088
44,096
Slices
1,408
3,008
4,928
9,280
9,792
of
MULT_ANDs
Number
18,560
19,584
27,392
38,784
47,232
66,176
66,176
88,192
LUTs
9,856
2,816
6,016
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
of
8
Table 20
www.xilinx.com
SelectRAM or Shift
Max Distributed
shows the available resources in all CLBs.
Carry-Chains
Register (bits)
Arithmetic &
1,058,816
1,058,816
1,411,072
157,696
296,960
313,334
438,272
620,544
755,712
45,056
96,256
Configuration
Virtex-II Pro block SelectRAM+ supports various configura-
tions, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 21: Dual- and Single-Port Configurations
Single-Port Configuration
As a single-port RAM, the block SelectRAM+ has access to
the 18 Kb memory locations in any of the 2K x 9-bit,
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
2
16K x 1 bit
8K x 2 bits
4K x 4 bits
Chains
SOP
2
Flip-Flops
Number
18,560
18,560
27,392
38,784
47,232
66,176
66,176
88,192
2,816
6,016
9,856
of
SelectRAM+
Distributed
128 bits
Carry-Chains
Number
116
140
164
164
188
68
44
44
92
92
92
of
512 x 36 bits
Registers
1K x 18 bits
2K x 9 bits
128 bits
Shift
(1)
Module 2 of 4
Chains
Number
of SOP
Table
112
112
160
176
176
208
208
240
80
TBUF
32
80
2
(1)
21.
44

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