XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 39

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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Table 11: LVCMOS Programmable Currents (Sink and Source)
Figure 23
tions. HSTL can sink current up to 48 mA. (HSTL IV)
All pads are protected against damage from electrostatic
discharge
Virtex-II Pro uses two memory cells to control the configura-
tion of an I/O as an input. This is to reduce the probability of
an I/O configured as an input from flipping to an output
when subjected to a single event upset (SEU) in space
applications.
Prior to configuration, all outputs not involved in configura-
tion are forced into their high-impedance state. The
pull-down resistors and the weak-keeper circuits are inac-
tive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
set High, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is set Low, the pull-up resistors are
activated on user I/O pins.
All Virtex-II Pro IOBs (except RocketIO transceiver pins)
support IEEE 1149.1 and IEEE 1532 compatible Bound-
ary-Scan testing.
DS083 (v4.7) November 5, 2007
Product Specification
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
SelectIO-Ultra
Figure 23: SSTL or HSTL SelectIO-Ultra Standards
shows the SSTL2, SSTL18, and HSTL configura-
OBUF
R
(ESD)
and
V CCO
2 mA
2 mA
2 mA
2 mA
2 mA
V REF
from
Clamp
Diode
over-voltage
4 mA
4 mA
4 mA
4 mA
4 mA
Programmable Current (Worst-Case Guaranteed Minimum)
V CCAUX = 2.5V
V CCINT = 1.5V
DS031_24_100900
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
PAD
transients.
www.xilinx.com
6 mA
6 mA
6 mA
6 mA
6 mA
Input Path
The Virtex-II Pro IOB input path routes input signals directly
to internal logic and / or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II Pro device, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V
constraints on which standards can be used in the same
bank. See I/O banking description.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output and / or the
3-state signal can be routed to the buffer directly from the
internal logic or through an output / 3-state flip-flop or latch,
or through the DDR output / 3-state registers.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most sig-
naling standards, the output High voltage depends on an
externally supplied V
imposes constraints on which standards can be used in the
same bank. See I/O banking description.
I/O Banking
Some of the I/O standards described above require V
and V
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in
bank has multiple V
nected to the same voltage. This voltage is determined by
the output standards in use.
8 mA
8 mA
8 mA
8 mA
8 mA
REF
voltages. These voltages are externally supplied
12 mA
12 mA
12 mA
12 mA
12 mA
REF
CCO
CCO
. The need to supply V
voltage. The need to supply V
pins, all of which must be con-
Figure 24
16 mA
16 mA
16 mA
16 mA
16 mA
and
Figure
REF
Module 2 of 4
24 mA
24 mA
24 mA
n/a
n/a
25. Each
imposes
CCO
CCO
28

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