XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 58

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XC2VP7-5FF672C

Manufacturer Part Number
XC2VP7-5FF672C
Description
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC2VP7-5FF672C

Package
672FCBGA
Family Name
Virtex-II Pro™
Device Logic Units
11088
Number Of Registers
9856
Maximum Internal Frequency
1050 MHz
Typical Operating Supply Voltage
1.5 V
Maximum Number Of User I/os
396
Ram Bits
811008

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3. NO_CHANGE
The NO_CHANGE option maintains the content of the out-
put registers, regardless of the write operation. The clock
edge during the write mode has no effect on the content of
the data output register DO. When the port is configured as
NO_CHANGE, only a read operation loads a new value in
the output register DO, as shown in
Control Pins and Attributes
Virtex-II Pro SelectRAM+ memory has two independent
ports with the control signals described in
trol inputs including the clock have an optional inversion.
Table 24: Control Functions
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM+ resource is config-
ured as dual-port RAM.
Total Amount of SelectRAM+ Memory
Virtex-II Pro SelectRAM+ memory blocks are organized in
multiple columns. The number of blocks per column
depends on the row size, the number of Processor Blocks,
and the number of RocketIO transceivers.
DS083 (v4.7) November 5, 2007
Product Specification
RAM Contents
Control Signal
Data_out
Address
Data_in
Data_in
CLK
SSR
WE
CLK
EN
WE
R
Figure 51: NO_CHANGE Mode
DI
New
Old
aa
Read and Write Clock
Enable affects Read, Write, Set, Reset
Write Enable
Set DO register to SRVAL (attribute)
Internal
Memory
Last Read Cycle Content (no change)
DO
Function
Figure
No change during write
Table
New
51.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
DS083-2_12_050901
24. All con-
www.xilinx.com
Table 25
amount of block SelectRAM+ memory available for each
Virtex-II Pro device. The 18 Kb SelectRAM+ blocks are
cascadable to implement deeper or wider single- or dual-port
memory resources.
Table 25: Virtex-II Pro SelectRAM+ Memory Available
Figure 52
XC2VP4 device.
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VPX20
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
Device
Figure 52: XC2VP4 Block RAM Column Layout
BRAM
Multiplier
Blocks
shows the number of columns as well as the total
shows the layout of the block RAM columns in the
Columns
DCM
DCM
10
12
14
14
16
4
4
6
8
8
8
CLBs
Serial Transceivers
Serial Transceivers
Blocks
Total SelectRAM+ Memory
RocketIO
136
192
232
328
308
444
RocketIO
12
28
44
88
88
CLBs
TM
TM
PPC405
in Kb
1,584
2,448
1,584
3,456
4,176
5,904
5,544
7,992
CLBs
CPU
216
504
792
DS083-2_11_010802
DCM
DCM
Module 2 of 4
1,622,016
2,506,752
1,622,016
3,538,944
4,276,224
6,045,696
5,677,056
8,183,808
221,184
516,096
811,008
in Bits
47

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