XC2VP7-5FF672C Xilinx Inc, XC2VP7-5FF672C Datasheet - Page 13
Manufacturer Part Number
FPGA Virtex-II Pro™ Family 11088 Cells 1050MHz 0.13um/90nm (CMOS) Technology 1.5V 672-Pin FCBGA
Specifications of XC2VP7-5FF672C
Device Logic Units
Number Of Registers
Maximum Internal Frequency
Typical Operating Supply Voltage
Maximum Number Of User I/os
Functional Description: RocketIO X Multi-Gigabit Transceiver (MGT)
This section summarizes the features of the RocketIO X
multi-gigabit transceiver. For an in-depth discussion of the
RocketIO X MGT, including digital and analog design con-
siderations, refer to the
RocketIO X Overview
Either eight or twenty RocketIO X MGTs are available on
the XC2VPX20 and XC2VPX70 devices, respectively. The
XC2VPX20 MGT is designed to operate at any baud rate in
the range of 2.488 Gb/s to 6.25 Gb/s per channel. This
includes specific baud rates used by various standards as
4.25 Gb/s per channel.
The RocketIO X MGT consists of the Physical Media
Attachment (PMA) and Physical Coding Sublayer (PCS).
The PMA contains the 6.25 Gb/s serializer/deserializer
(SERDES), TX/RX buffers, clock generator, and clock
recovery circuitry. The RocketIO X PCS has been signifi-
cantly updated relative to the RocketIO PCS. In addition to
the existing RocketIO PCS features, the RocketIO X PCS
features 64B/66B encoder/decoder/scrambler/descrambler
and SONET compatibility.
The RocketIO X transceiver is implemented in Current
Mode Logic (CML). A CML transmitter output consists of
transistors configured as shown in
positive supply and offers easy interface requirements. In
this configuration, both legs of the driver, VP and VN, sink
current, with one leg always sinking more current than its
complement. The CML output consists of a differential pair
with 50Ω source resistors. The signal swing is created by
switching the current in a common-source differential pair.
DS083 (v4.7) November 5, 2007
Figure 2: CML Output Configuration
1. The XC2VPX70 MGT operates at a fixed
CML Output Driver
RocketIO X Transceiver User
2. CML uses a
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
between the RocketIO X PMA/PCS and the RocketIO
Figure 4, page 3
RocketIO X transceiver and its FPGA interface signals.
Table 1: Communications Standards Supported by
RocketIO X Transceiver
On-chip termination is provided at the transmitter, eliminat-
ing the need for external termination. The output driver and
termination are powered by V
uses a CML approach with 50Ω termination to TXP and
TXN as shown in
2. XC2VPX70 operates at a fixed 4.25 Gb/s baud rate.
XAUI (10-Gb Ethernet)
(10-Gb Fibre Channel)
Aurora (Xilinx protocol)
One channel is considered to be one transceiver.
Table 7, page
Figure 3: RocketIO X Transmit Termination
shows a high-level block diagram of the
17, for a summary of the differences
1, 2, 4, 8, 16
1, 2, 3, 4,...
1, 2, 3, 4,...
1, 4, 12
at 1.5V. This configuration
I/O Bit Rate
2.488 to 6.25
2.488 to 6.25
Module 2 of 4