L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet
L-ET4148-50C-DB
Specifications of L-ET4148-50C-DB
Related parts for L-ET4148-50C-DB
L-ET4148-50C-DB Summary of contents
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Features Forty-eight 10/100/1000 Mbits/s Ethernet ports: ■ — Forty-four-ports supporting 6-pin SGMII inter- faces to GbE copper PHYs — Four combo ports supporting either SGMII inter- face or SerDes interface Two 10 Gbits/s Ethernet ports with XAUI interfaces: ■ ...
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... L2 MAC address and TCP/IP layer provisioning. Each port supports up to eight traffic class queues. Each packet is assigned to a class queue based on the 802.1p coding or IP TOS/DSCP. Incoming traffic is policed to ensure the optimum use of network resources. Outgoing traffic is scheduled or shaped according to the traffic class and network resource usage ...
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... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Contents Features .................................................................................................................................................................... 1 Benefits ..................................................................................................................................................................... 1 Target Applications ................................................................................................................................................... 1 Block Diagram........................................................................................................................................................... 1 Description ................................................................................................................................................................ 2 System Diagram........................................................................................................................................................ 2 Pin Descriptions ........................................................................................................................................................ 8 Memory Map ........................................................................................................................................................... 14 Functional Description............................................................................................................................................. 20 Packet Reception.............................................................................................................................................. 20 VLAN Assignment............................................................................................................................................. 22 Access Control.................................................................................................................................................. 24 Bridging............................................................................................................................................................. 26 Flow Identification ............................................................................................................................................ 30 Policing ............................................................................................................................................................. 31 Storage ............................................................................................................................................................. 33 Retrieval............................................................................................................................................................ 34 VLAN Encapsulation......................................................................................................................................... 36 Packet Transmission ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Contents Acl_Ip_Key_Table_1 ......................................................................................................................................... 77 Acl_Ip_Key_Table_2 ......................................................................................................................................... 78 Acl_Ip_Key_Table_3 ......................................................................................................................................... 79 Acl_Ip_Key_Table_4 ......................................................................................................................................... 80 Acl_Ip_Key_Table_5 ......................................................................................................................................... 81 Acl_Ip_Key_Table_6 ......................................................................................................................................... 82 Acl_Ip_Key_Table_7 ......................................................................................................................................... 83 Acl_Ip_Key_Table_8 ......................................................................................................................................... 84 Acl_Mode .......................................................................................................................................................... 86 Acl_Port_Ace_Map_Index_Table ..................................................................................................................... 87 Acl_Port_Ace_Map_Table ................................................................................................................................ 88 Acl_Priority_Update_En .................................................................................................................................... 89 Acl_Protocol_Ace_Map_Index_Table ............................................................................................................... 90 Acl_Protocol_Ace_Map_Table.......................................................................................................................... 91 Acl_Protocol_Table ........................................................................................................................................... 92 Acl_Result_Table .............................................................................................................................................. 93 Acl_Tcp_Key_Table_0 ...................................................................................................................................... 94 Acl_Tcp_Key_Table_1 ...................................................................................................................................... 95 Acl_Tcp_Key_Table_2 ...................................................................................................................................... 96 Acl_Tcp_Key_Table_3 ...................................................................................................................................... 97 Acl_Tcp_Key_Table_4 ...................................................................................................................................... 98 Acl_Vlan_Index_Table ...................................................................................................................................... 99 Device_Version ...............................................................................................................................................100 Layer_2_Active_Port_Map..............................................................................................................................101 Layer_2_Aggregation_Mask_Table ................................................................................................................102 Layer_2_Blocking_Mask .................................................................................................................................103 Layer_2_Current_Time ...................................................................................................................................104 Layer_2_Dest_Map_Table..............................................................................................................................105 Layer_2_Dest_Mirror_Map ...
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... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Contents Layer_2_User_Port_Snooping_Port............................................................................................................... 130 Layer_2_Vlan_Mask_Table ............................................................................................................................ 131 Layer_2_Vlan_Port_State_Table.................................................................................................................... 132 Mac_Global_Mode.......................................................................................................................................... 133 Mac_Mode_{0..4}............................................................................................................................................ 135 Mac_Mode_{5..6}............................................................................................................................................ 138 Mac_Status_{0..4} .......................................................................................................................................... 140 Mdio_Control .................................................................................................................................................. 141 Mdio_Mode ..................................................................................................................................................... 144 Mdio_Status.................................................................................................................................................... 146 Multicast_Rate_Accumulator .......................................................................................................................... 147 Multicast_Rate_Decrement_Period ................................................................................................................ 148 Multicast_Rate_Discard_Mask ....................................................................................................................... 149 Multicast_Rate_Limit ...................................................................................................................................... 150 Multicast_Rate_Limit_Events ......................................................................................................................... 151 Multicast_Rate_Mode ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Contents Policer_Delta_Table_{5..6} .............................................................................................................................193 Policer_Flow_Id_Table_{0..4} .........................................................................................................................194 Policer_Flow_Id_Table_{5..6} .........................................................................................................................195 Policer_Flow_Mode_Table_{0..4} ...................................................................................................................196 Policer_Flow_Mode_Table_{5..6} ...................................................................................................................197 Policer_Limit_Table_{0..4} ..............................................................................................................................198 Policer_Limit_Table_{5..6} ..............................................................................................................................199 Policer_Mode_{0..4}........................................................................................................................................200 Policer_Mode_{5..6}........................................................................................................................................201 Policer_Statistics_{0..4} ..................................................................................................................................202 Policer_Statistics_{5..6} ..................................................................................................................................203 Port_Mode_{0..4} ............................................................................................................................................204 Port_Mode_{5..6} ............................................................................................................................................208 Priority_Decode_Table_{0..4} .........................................................................................................................211 Priority_Decode_Table_{5..6} .........................................................................................................................212 Priority_Encode_Table_{0..4} .........................................................................................................................213 Priority_Encode_Table_{5..6} .........................................................................................................................214 Rx_Bytes ...
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... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Contents Vlan_Index_Table_{0..4} ................................................................................................................................ 262 Vlan_Index_Table_{5..6} ................................................................................................................................ 263 Vlan_Port_Protocol_Table_{0..4} ................................................................................................................... 264 Vlan_Port_Protocol_Table_{5..6} ................................................................................................................... 265 Appendix B: Configuration .................................................................................................................................... 266 General ........................................................................................................................................................... 266 Packet Buffer .................................................................................................................................................. 266 Ethernet Interfaces ......................................................................................................................................... 266 Bridging........................................................................................................................................................... 273 Access Control Lists ....................................................................................................................................... 280 Quality of Service............................................................................................................................................ 285 Other Networking Functions ........................................................................................................................... 290 Statistics ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Pin Descriptions The ET4148-50 pins are summarized in the following series of tables. Each table is dedicated to a single interface type. Table 1. 1 Gbit/s Ethernet SGMII Pins Pin Name Type RXCLK(47:00)_(P/N) LVDS 47{AL13, AL12}, 46{AF13, AF12}, 45{AL11, AL10}, 44{AJ10, ...
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... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Pin Descriptions (continued) Table 2. 1 Gbit/s Ethernet SFP Pins Pin Name Type RXSSD(47:44)_(P,N) CML input 47{AJ19, AJ20}, 46{AL18, AL19}, TXSSD(47:44)_(P,N) CML output REFCLK_3_(P,N) CML input {AJ14, AJ15} RESP_3 REF VSSRESP_3 REF Table 3 ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Pin Descriptions (continued) Table 4. Supervisor PCI Pins Pin Name Type PCI_RST_N CMOS input PCI_CLK CMOS input AD(31:0) CMOS I/O CBE[3:0]_N CMOS I/O PAR CMOS I/O FRAME_N CMOS I/O IRDY_N CMOS I/O TRDY_N CMOS I/O ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Pin Descriptions (continued) Table 5. Miscellaneous Pins Pin Name Type TDI CMOS input TCK CMOS input TMS CMOS input TRST_N CMOS input TDO CMOS output C31 MDIO_C22_(1:0) CMOS I/O (open drain) ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Pin Descriptions (continued) Table 6. Power and Ground Pin Name Type VDD12_CORE PWR M15, M13, M11, L20, L18, L16, L14, L12, AA20, AA14, AA12, P13, P11, N20, N18, N16, N14, N12, M21, M19, M17, T15, T13, T11, R18, R16, R14, ...
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... April 2006 Memory Map The following table lists all of the ET4148-50’s registers in the order that they appear in the address space allo- cated to the device. The base addresses listed below must be added to the base address configured for the device in order to arrive at the actual physical address of each register. ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Memory Map (continued) Table 7. Memory Map (continued) Base Address Size 0x0004_d600 512 0x0004_d800 512 0x0004_da00 512 0x0004_dc00 512 0x0004_de00 256 0x0004_df00 128 0x0004_df80 0x0004_dfc0 0x0004_dfd0 0x0004_dfe0 0x0004_e000 1024 0x0005_0000 16384 0x0005_4000 4096 0x0005_5000 1024 0x0005_5400 ...
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... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Memory Map (continued) Table 7. Memory Map (continued) Base Address Size 0x0006_5000 1024 0x0006_5400 512 0x0006_5600 512 0x0006_5800 512 0x0006_5a00 512 0x0006_5c00 512 0x0006_5e00 256 0x0006_5f00 128 0x0006_5f80 0x0006_5fc0 0x0006_5fd0 0x0006_5fe0 ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Memory Map (continued) Table 7. Memory Map (continued) Base Address Size 0x0007_8000 16384 0x0007_c000 4096 0x0007_d000 1024 0x0007_d400 512 0x0007_d600 512 0x0007_d800 512 0x0007_da00 512 0x0007_dc00 0x0007_de00 256 0x0007_df00 128 0x0007_df80 0x0007_dfc0 0x0007_dfd0 0x0007_dfe0 0x0007_e000 1024 ...
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... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Memory Map (continued) Table 7. Memory Map (continued) Base Address Size 0x000c_467c 0x000c_4680 0x000c_4700 244 0x000c_4800 0x000c_4808 0x000c_480c 0x000c_4810 0x000c_4814 0x000c_4818 0x000c_8000 0x000c_8050 0x000c_8080 0x000c_80d0 0x000c_8100 0x000c_8150 0x000c_8180 0x000c_81d0 0x000c_8200 0x000c_8240 ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Memory Map (continued) Table 7. Memory Map (continued) Base Address Size 0x000c_bb84 0x000c_bb88 0x000c_bc00 0x000c_bc40 0x000c_bc48 0x000c_bc50 0x000c_bc58 0x000c_bc5c 0x000c_bc60 0x000c_bc64 0x000c_bc68 0x000c_bd00 192 0x000c_c400 0x000c_c440 0x000c_c448 0x000c_c44c 0x000c_c450 0x000c_c454 0x000c_c458 0x000c_c45c 0x000c_c460 0x000c_c464 0x000c_c468 0x000c_c46c ...
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... The packet reception process is rather straight forward receive packet is a flow-control packet and flow control is enabled, an indication is provided to the MAC’s corresponding transmit function that causes it to cease transmit- ting for a specified period of time. All other packets are parsed and then passed along to the VLAN assignment process. ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Functional Description (continued) Packet Reception (continued) ETHERNET V2 IP (v4 or v6) TCP/UDP The packet reception process automatically restarts after each packet. 20 IEEE 802.3 SNAP ETHERNET V2 IEEE 802.3 SNAP IP (v4 or v6) IEEE 802.1Q TCP/UDP IP (v4 or v6) TCP/UDP Figure 4 ...
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... Figure 5. VLAN Assignment Process—Revisions B and B1 In version B and B1, VLAN tagged packets may only be received by those Ethernet ports that are configured as trunk ports tagged packet is received via an access port discarded. In version C, VLAN tagged packets may be received by either access-configured or trunk-configured Ethernet ports. The VLAN identifiers in tagged packets must also exist in the ET4148-50's VLAN index table ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Functional Description (continued) VLAN Assignment (continued) Y USE PORT/ETHERTYPE TO ASSIGN VLAN ID DELIVER PACKET TO ACCESS CONTROL Figure 6. VLAN Assignment Process—Revision C 22 DISCARD N INVALID VLAN IDs? Y ETHERTYPE DEFINED FOR RECEIVE PORT? N USE DEFAULT PORT VLAN ID DISCARD PACKET ...
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... Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Functional Description (continued) Access Control The access control process examines certain fields within each receive packet and determines whether or not the packets should be granted access to the ET4148-50 and its attached networks. START VLAN-BASED ACLS? ...
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... The leftmost bit in the resulting ACE map indi- cates the first ACE in the ACL that matches all of the criteria. In the case where multiple ACEs match the against the receive packet the one that appears first in the ACL that is applied to the receive packet. ...
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... Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Functional Description (continued) Bridging The ET4148-50’s bridging process utilizes Layer 2 information from the packet as a primary means for determining the destination or destinations of a receive packet. FOR LOOK-UP, GET EXPECTED RECEIVE PORT APPLY BLOCKING MASK B Agere Systems Inc ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Functional Description (continued) Bridging (continued) B EXCESSIVE Y MULTICAST PACKET RATE? N APPLY MULTICAST RATE MASK 26 A TCP DEST == USER Y && SNOOPING ENABLED? N SUPERVISOR N RECEIVE VLAN == ROUTING TRANSMIT ENABLED? VLAN APPLY VLAN MASK APPLY PORT AGGREGATION MASK ...
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... If the VLAN associated with the receive packet does not match the VLANs associated with any of the destination ports indicated in the destination map so far, then the packet is not going to be forwarded due to VLAN filtering. However enabled, the supervisor may receive these VLAN-filtered packet so that it may apply routing opera- tions to these packets and allow them to communicate across VLAN boundaries. The supervisor’ ...
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... It is presumed that all ports are a member of an aggregate. An aggregate may be as small as a single port. In this case, the single port in the aggregate would never be eliminated by any of the aggregation masks. For multiport aggregates, each aggregate mask eliminates all but one destination port for all of the aggregates configured in the device ...
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... All receive packets are assigned to one flow or another. Packets received via one of the 10/100/1000 Mbits/s Ethernet ports are assigned to one of eight flows per port. Packets received via one of the 10 Gbits/s ports are assigned to one of eighty flows per port. Each flow is associated with a policer that may be configured to limit the total bandwidth of the flows. ...
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... This delay interval is proportional to the operating speed of the associated receive port. i.e., the interval for a 10 Mbits/s port is 100 times that Gbit/s port. This automatic proportional behavior means that the delta that is periodically applied to the accumulator can be reasonably thought percentage of available bandwidth. The delta is adjusted as desired during configuration to establish the maximum receive bandwidth allowed for the asso- ciated traffic flow ...
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... If the aggregate byte rate is greater than the band- width permitted by the leak delta, then the value in the accumulator will tend to increase. The traffic flow is not con- sidered out of profile until the value in the accumulator exceeds the user-defined accumulator limit. The setting of this limit establishes the policer’ ...
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... The remainder of the storage process entails the actual storage of the packet into the allocated buffers, mapping the packet’s priority level (16 levels) to one of the eight queues that exist per transmit port. Finally, the queue map- ping and the destination map are used to identify the various individual queues into which a reference to the stored packet is deposited ...
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... Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Functional Description (continued) Retrieval Two processes per queue operate in parallel during packet retrieval. One process manages a bandwidth shaper function while the other performs arbitration and actually retrieves the stored packet. START ADD CREDIT TO TOKEN BUCKET ACCUMULATOR ...
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... Packets may be destined for multiple queues or ports. This being the case, not every packet retrieval results in the deallocation of the buffer used for packet storage. Only after the completion of the last retrieval of a packet may its buffers be deallocated and made available for future storage operations. ...
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... If the packet was tagged, it will be transmit- ted with the same VLAN tag, and the COS will not be updated. If the packet was untagged, it will be transmitted without a VLAN tag. In both cases, the IP DSCP will not be updated. ...
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... The behavior of a trunk port is a bit more complex. An optional mode is available for the ET4148-50 whereby pack- ets are transmitted on a trunk port without a VLAN tag if the VLAN that the packet belongs to matches the default VLAN ID of the transmit (trunk) port. If this mode is not in use, all packets transmitted by a trunk port are transmit- ted with a VLAN tag. ...
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... If a packet was modified during its traversal of the ET4148-50, a new CRC value is computed by the transmitting Ethernet MAC. Otherwise, the CRC received with the packet is used for transmission. ...
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... Typically, each queue is dedicated to a single purpose (e.g., source address learning limited range of purposes. The Layer 2 address tables may be configured to forward or copy any arbitrary MAC destination address to the supervisor. Also, certain types of packets are generally forwarded or copied to the supervisor. These packet types include those with unknown MAC source addresses, IGMP packets, ACL logged packets, and others. Generally, each of the supervisor’ ...
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... FIFO PHYSICAL END Figure 17. Receive Circular FIFO Structure The discontinuity caused by the gap left at the end of the physical range of the FIFO is handled by means of a 32-bit pointer that is written to the FIFO as the first word of the packet’s data structure. The 32-bit pointer (Supervisor_Rx_Packet ...
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... Supervisor Packet Reception Packet Reception Process Packets received by the physical Ethernet interfaces may be forwarded or copied to one or more of the queues dedicated to the supervisor. These forwarding and copying decisions are based on the contents of the packets. These supervisor queues are serviced in a normal manner. However, rather than being directed to Ethernet ports, these packets are directed to the supervisor via the PCI bus. The identity of each packet’ ...
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... The first step taken by the ET4148- determine if the space remaining between the logical end of a receive FIFO and its physical end (refer to Figure 18 on page 40 for a depiction of the terms) is great enough to accommo- date a maximum length packet. The following equation is used to make this determination: ( Supervisor_Rx_Fifo_Limits_{0..7}.rx_fifo_end_ptr[31:0] - Supervisor_Rx_Fifo_Ptr_{0..7}.wr_ptr[31:2] ) > ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Functional Description (continued) Supervisor Packet Reception Figure 19. Supervisor Packet Reception Process (Supervisor Actions Supervisor Actions. Upon detecting that Supervisor_Rx_Fifo_Status_{0..7}.not_empty is true, the super- visor reads Supervisor_Rx_Fifo_Ptr_{0..7}.first_ptr[31:2] in order to determine the location of the start of the first packet in the receive FIFO. ...
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... These faked look-up results are used to direct the packet to the queues associated with the transmit ports desired by the supervisor. Because of this requirement to preload the look-up results, the transmit packet data structure is headed by a series of fields that hold such information as a transmit port map, priority level, and the like. ...
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... Layer 3 headers that can be concatenated to form a packet’s header. Packet bodies may also be cataloged and warehoused in this fashion. Each packet descriptor block consists of a one or more pairs of 32-bit words. The first 32-bit word is a pointer to a packet segment. The second 32-bit word contains a byte count for the segment and a flag that indicates whether or not the current segment is the last segment for the packet ...
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... The ET4148-50 detects that Supervisor_Tx_Fifo_Ptr_{0..1}.rd_ptr[31:2] and Supervisor_Tx_Fifo_Ptr_{0..1}.last[31:2] are no longer equal and advances Supervisor_Tx_Fifo_Ptr_{0..1}.rd_ptr[31:2] to the next location within Supervisor_Tx_Fifo. This location is then read by the ET4148-50 to gather the pointer to the transmit packet’s descriptor block. Agere Systems Inc. (continued) START ...
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... Supervisor_Tx_Descriptor. The first segment of every transmit packet contains the destination port map and priority information for the packet. The packet segments are stored as a contiguous packet within the ET4148-50 in the normal manner and queued for transmission utilizing the supplied destination information. ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Data Structures Supervisor_Rx_Fifo_{0..7} Description: An assortment of receive packets. Table 8. Supervisor_Rx_Fifo_{0..7} Register Parameters Parameter Base Address Structure Size Structure Instances Structure Spacing Figure 22. Supervisor_Rx_Fifo_{0..7} Data Structure This data structure is a collection of Supervisor_Rx_Packet data structures. ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Data Structures (continued) Supervisor_Rx_Packet Description: The form of received packets in supervisor memory space. Table 9. Supervisor_Rx_Packet Register Parameters Parameter Base Address One 32-bit word after the previous Supervisor_Rx_Packet Structure Size Variable Structure Instances Variable Structure Spacing ...
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... FIFO structure maintained within the supervisor’s memory. The first word of Supervisor_Rx_Packet always immediately follows the last word of the previous instance. The first word of this data structure is a pointer to the remainder of the data structure. Ordinarily, these structures are arranged contiguously. If the space at the end of Supervisor_Rx_Fifo{0..7} is insufficient to accommo- date a maximum length packet, then Supervisor_Rx_Packet ...
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... This data structure is a list of descriptors of packet segments. Each packet segment requires its own descriptor. The descriptors are processed in the order in which they are encountered in Supervisor_Tx_Descriptor. Each packet requires a Supervisor_Tx_Descriptor structure with at least one record. Transmit packet processing is terminated upon the completion of processing of the record whose last bit is asserted ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Data Structures (continued) Supervisor_Tx_Fifo_{0..1} Descriptions: FIFO list of transmit descriptor block pointers. Table 13. Supervisor_Tx_Fifo_{0..1} Register Parameters Parameter Base Address Supervisor_Tx_Fifo_Limits_{0..1}.start_ptr[31:2] Structure Size Supervisor_Tx_Fifo_Limits_{0..1}.end_ptr[31:2] - Supervisor_Tx_Fifo_Limits_{0..1}.start_ptr[31: Structure Instances Structure Spacing ...
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... This data structure is a single transmit packet. Every transmit packet is preceded by a priority[3:0] value and a dest_map[57:0] vector. The packet data bytes start at byte offset 8 and continue from there. The byte located at offset 8 must always be the first byte of packet’s 48-bit Layer 2 destination address field. ...
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... Base Address Supervisor_Tx_Descriptor.tx_segment_ptr[31:0] Structure Size Supervisor_Tx_Descriptor.tx_segment_length[13:0] Structure Instances Structure Spacing Figure 27. Supervisor_Tx_Packet_Segment Data Structure This data structure is a single segment of a packet. One or more segments are used to assemble transmit packets. Agere Systems Inc. Value Variable Variable Supervisor_Tx_Packet segment Agere Systems - Proprietary ...
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... Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Electrical Specifications (continued) Recommended Operating Conditions Table 20. Recommended Operating Conditions* Parameter Core Supply Voltage Core PLL Voltage SGMII Termination Voltage SGMII I/O Voltage SGMII PLL Voltage SFP Output Buffer Voltage ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Electrical Specifications (continued) Thermal Characteristics Table 22. Thermal Characteristics Parameter Junction Temperature Theta Junction to Case Theta Case to Ambient Required by Heat Sink PCI I/O Specification Table 23. dc Electrical Specification—PCI Parameter Symbol Pin Type Input High Voltage ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Electrical Specifications (continued) SGMII I/O Transmit Specifications Table 25. SGMII I/O Transmit Specifications Parameter High Output Voltage Low Output Voltage Peak-to-peak Output Differential Voltage Output Offset Voltage (common-mode voltage) Output Overshoot/Undershoot ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Electrical Specifications (continued) SFP—1.25 Gbits/s SerDes Specifications Table 27. RX Serial Buffer Input Electrical Specification—1.25 Gbits/s SerDes I/O Parameter Symbol Differential Input V ID Voltage Common-mode Input V IC Voltage Input Resistance R I Receiver Rise and ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Electrical Specifications (continued) SFP—1.25 Gbits/s SerDes Specifications Table 29. TX Serial Buffer Output Electrical Specification—1.25 Gbits/s SerDes I/O Parameter Symbol Pin Type Transmit Differential V ODAC Voltage Swing Transmit Differential ...
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... Table 30. Clocking and Timing Specifications Parameter Transmitter Output Jitter in Half-Rate Mode: Deterministic Random Total* * Does not include in-band reference-clock jitter, which must be added to this. In-band jitter is defined as jitter with spectral content within the 3 dB closed-loop bandwidth of the PPL –A1 –A2 Table 31. Transmitter Eye Diagram Values ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Electrical Specifications (continued) 10G—3.125 Gbits/s SerDes Specifications Table 32. RX Serial Buffer Input Electrical Specification—3.125 Gbits/s SerDes I/O Parameter Symbol Differential Input V ID Voltage Common-mode Input V IC Voltage Input Resistance ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Electrical Specifications (continued) 10G—3.125 Gbits/s SerDes Specifications Table 34. TX Serial Buffer Output Electrical Specification—3.125 Gbits/s SerDes I/O Parameter Symbol Pin Type Transmit Differential V ODAC Voltage Swing Transmit Differential V ODDC Voltage Swing Transmit Differential ...
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... Table 35. Clocking and Timing Specifications Parameter Transmitter Output Jitter in Half-Rate Mode: Deterministic Random Total* * Does not include in-band reference-clock jitter, which must be added to this. In-band jitter is defined as jitter with spectral content within the 3 dB closed-loop bandwidth of the PPL –A1 –A2 Table 36. Transmitter Eye Diagram Values ...
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... Vcc 0.4 Vcc 0.3 Vcc Table 38. 3.3 V PCI Clock ac Specification Parameter Clock Cycle Time Clock High Time Clock Low Time Clock Slew Rate Rise and Fall Time* * Test conditions, 30%—60 load plus pad and package C, 140 Ω SETUP HOLD SETUP HOLD ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Electrical Specifications (continued) Timing Diagrams (continued) PCI (continued) OUTPUT DELAY DELAY TRISTATE OUTPUT Table 39. 3.3 V PCI Clock ac Specification Parameter Clock-to-signal Valid Float-to-active Delay Active-to-float Delay Setup Time Hold Time Agere Systems Inc. ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Electrical Specifications (continued) Timing Diagrams (continued) SFP SerDes I/O Clock Input Specification Table 40. SFP SerDes Reference Clock Specifications Parameter Clock Frequency—SFP (REFCLK_3) Frequency Stability Duty Cycle Rise Time and Fall Time (20%—80%) Differential Amplitude ...
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... April 2006 Electrical Specifications (continued) Timing Diagrams (continued) Core Clock Input Specifications This pertains to signals named REFCLK_CORE and the supporting PLL voltage pins, AVDD_PLL_CORE and AGND_PLL_CORE. Table 42. Core Clock Input Specifications Parameter Maximum Input Voltage Minimum Input Voltage Input High Voltage ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Electrical Specifications (continued) Timing Diagrams (continued) SGMII PLL Timing and Clocking Specification Table 43. SGMII PLL Timing and Clocking Specification Parameter Maximum Input Voltage Minimum Input Voltage Input High Voltage Input Low Voltage Input Hysteresis ...
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... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Electrical Specifications (continued) Timing Diagrams (continued) JTAG Timing Table 45. JTAG Timing Parameter TCK Period TCK High TCK Low TDI, TMS to TCK Setup TDI, TMS to TCK Hold TCK to TDO Delay Agere Systems Inc. ...
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... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Physical Dimensions B, B1, C 3.22 MAX Revision DIM “A” THICKNESS SCHEDULE Figure 37. ET4148-50 Physical Dimensions 70 40.00 SQUARE BOTTOM VIEW 1.08 NOM 2.46 ± 0.30 DIM “B” DIM “C” Agere Systems - Proprietary Preliminary Data Sheet ...
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... Proper operation of the line cache depends upon the data being written to a register’s wide record in a particular order: from offset zero to the last 32-bit word of the record. When the supervisor performs a write to the last offset of the record, the line cache is automatically written to the desired register record as a single, wide word ...
Page 72
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Acl_Deny_Packets Description: The number of packets denied access by the ACL function. Table 46. Acl_Deny_Packets Register Parameters Parameter Base Address 0x0004_2508 Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Table 47. Acl_Deny_Packets Field Parameters ...
Page 73
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Acl_En Description: Enables the individual ACLs. Table 48. Acl_En Register Parameters Parameter Value Base Address 0x0004_2500 Register Size 8 Register Instances 1 Register Spacing NA Record Size 8 Record Instances 1 Record Spacing ...
Page 74
... This table is addressed by the concatenation of the acl_index[5:0] value and the IP address look-up result (ip_addr_index[8:0]). Each entry in this table is a 10-bit index into Acl_Ip_Addr_Ace_Map_Table. This table allows the 512 IP addresses appearing in 64 ACLs to address as many as 1,024 ACE maps. The follow- ing figure shows where this table fits in the processing pipeline. ...
Page 75
... This table is addressed by Acl_Ip_Addr_Ace_Map_Index_Table.ip_addr_ace_map_index[9:0] and returns the 64-bit ACE map value for the associated IP address. An ACE map is a vector that identifies all of the ACEs for which the associated IP address generates a match. The following figure shows where this table fits in the ACL processing pipeline. ...
Page 76
... This first stage of IP address look-up utilizes just a single record. Either three IPv4 address keys or one IPv6 address key is stored here. The comparisons result in an index computation. For IPv4, one of four index values are chosen. For IPv6, one of two index values are chosen. In both cases, these index values are used to address records in the next stage of the look-up ...
Page 77
... Record Instances Record Spacing Figure 46. Acl_Ip_Key_Table_1 Register Diagram Table 57. Acl_Ip_Key_Table_1 Field Parameters Field Name ipv4_key_{}{0..2}[31:0] ipv6_key[127:0] This second stage of IP address look-up utilizes two records for IPv4/IPv6 or four records for IPv4-only. Agere Systems Inc. Value 0x0004_2480 ipv4_key_0[31:0] or ipv6_key[127:96] ipv4_key_1[31:0] or ipv6_key[95:64] ...
Page 78
... Record Size Record Instances Record Spacing Figure 47. Acl_Ip_Key_Table_2 Register Diagram Table 59. Acl_Ip_Key_Table_2 Field Parameters Field Name ipv4_key_{0..2}[31:0] ipv6_key[127:0] This third stage of IP address look-up utilizes four records for IPv4/IPv6 or 16 records for IPv4-only. 78 Value 256 ipv4_key_0[31:0] or ipv6_key[127:96] ipv4_key_1[31:0] or ipv6_key[95:64] ipv4_key_2[31:0] or ipv6_key[63:32] ...
Page 79
... Record Size Record Instances Record Spacing Figure 48. Acl_Ip_Key_Table_3 Register Diagram Table 61. Acl_Ip_Key_Table_3 Field Parameters Field Name ipv4_key_{0..2}[31:0] ipv6_key[127:0] This fourth stage of IP address look-up utilizes eight records for IPv4/IPv6 or 64 records for IPv4-only. Agere Systems Inc. Value 0x0004_1c00 1024 ipv4_key_0[31:0] or ipv6_key[127:96] ...
Page 80
... Record Size Record Instances Record Spacing Figure 49. Acl_Ip_Key_Table_4 Register Diagram Table 63. Acl_Ip_Key_Table_4 Field Parameters Field Name ipv4_key_{0..2}[31:0] ipv6_key[127:0] This fifth stage of IP address look-up utilizes 16 records for IPv4/IPv6 or 256 records for IPv4-only. 80 Value 0x0003_e000 4096 256 ipv4_key_0[31:0] or ipv6_key[127:96] ipv4_key_1[31:0] or ipv6_key[95:64] ...
Page 81
... Field Name ipv4_key[31:0] ipv4_result_{0..1}[23:0] ipv6_key[127:0] This sixth stage of IP address look-up marks the end of processing for IPv4 addresses. This stage utilizes 32 records for IPv4/IPv6 or 1,024 records for IPv4-only. ipv4_result_{0..1}[23:0] utilizes the following format: { ip_src_addr_index_{0..1}[8:0], ip_src_addr_flow_id_{0..1}[2:0], ip_dest_addr_index_{0..1}[8:0], ip_dest_addr_flow_id_{0..1}[2:0] } Agere Systems Inc ...
Page 82
... Register Spacing Record Size Record Instances Record Spacing Figure 51. Acl_Ip_Key_Table_6 Register Diagram Table 67. Acl_Ip_Key_Table_6 Field Parameters Field Name ipv6_key[127:0] This seventh stage of IP address look-up operates only on IPv6 addresses. This stage utilizes 64 records for IPv6. 82 Value 0x0004_1800 1024 ipv6_key[127:96] ipv6_key[95:64] ipv6_key[63:32] ...
Page 83
... Record Size Record Instances Record Spacing Figure 52. Acl_Ip_Key_Table_7 Register Diagram Table 69. Acl_Ip_Key_Table_7 Field Parameters Field Name ipv6_key[127:0] This eighth stage of IP address look-up operates only on IPv6 addresses. This stage utilizes 128 records for IPv6. Agere Systems Inc. Value 2048 128 ipv6_key[127:96] ...
Page 84
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Acl_Ip_Key_Table_8 Description: This table performs the ninth and final stage of IP address look-up. Table 70. Acl_Ip_Key_Table_8 Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing ...
Page 85
... This final stage of IP address look-up operates only on IPv6 addresses. This stage utilizes 256 records of two IPv6 addresses each. Each record contains three possible sets of result values. Agere Systems Inc. Parameters Mode = R/W A 128-bit IPv6 address value ...
Page 86
... Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Table 73. Acl_Mode Register Field Parameters Field Name ipv4_only port_based_acls auto_deny_log_en This register provides a series of general configuration and mode bits for the ACL look-up function. 86 Value Figure 54. Acl_Mode Register Diagram Parameters ...
Page 87
... Each entry in this table is an 8-bit index into Acl_Protocol_Port_Ace_Map_Table. This table allows the 256 TCP port ranges appearing in 64 ACLs to address as many as 256 ACE maps. The fol- lowing figure shows where this table fits in the processing pipeline. Agere Systems Inc. ...
Page 88
... This table is addressed by Acl_Port_Ace_Map_Index_Table.port_ace_map_index[7:0] and returns the 64-bit ACE map value for the associated TCP port. An ACE map is a vector that identifies all of the ACEs for which the associated TCP port number range registers a match. The following figure shows where this table fits in the ACL processing pipeline. ...
Page 89
... Figure 59. Acl_Priority_Update_En Register Diagram Table 79. Acl_Priority_Update_En Field Parameters Field Name priority_update_en[60:0] Mode = R/W Offset = 0.3 Instances = 1 Reset = 0 This register provides a per-port method for enabling the classification-based replacement of packet priority val- ues. PORT XG1 XG0 SU1 REFERENCE Agere Systems Inc. Value 0x0004_2510 ...
Page 90
... This table is addressed by the concatenation of the acl_index[5:0] value and a protocol index value (acl_protocol_index[2:0]). Each entry in this table is a 7-bit index into Acl_Protocol_Port_Ace_Map_Table. This table allows the eight protocol indexes appearing in 64 ACLs to address as many as 256 ACE maps. The fol- lowing figure shows where this table fits in the processing pipeline. ACL Index ...
Page 91
... This table is addressed by Acl_Protocol_Ace_Map_Index_Table.protocol_ace_map_index[6:0] and returns the 64-bit ACE map value for the associated packet protocol. An ACE map is a vector that identifies all of the ACEs for which the associated protocol registers a match. The following figure shows where this table fits in the ACL processing pipeline. ...
Page 92
... Table 85. Acl_Protocol_Table Field Parameters Field Name acl_protocol[2:0] This table is addressed by a concatenation of ethertype_index[2:0] (derived from the packet’s Layer 2 type field) and ip_protocol_index[2:0] (derived from the packet’s Layer 3 protocol field). ethertype_index[2:0] makes up the most significant portion of the table’s address. This 6-bit concatenation is shifted left two bits in order to address 32-bit words ...
Page 93
... ACE). acl_index[5:0] occupies the upper portion of the concat- enated address word. ace_index[5: internal value (not accessible to the supervisor) that is derived from the priority encoding of the bitwise and of all of the ACE maps retrieved for a particular packet, hence, identifying the matching ACE. Agere Systems Inc. Value ...
Page 94
... Field Name tcp_key_0_{0..2}[15:0] This first stage of TCP port number look-up utilizes just a single record. Three TCP port number keys are stored here. The comparisons between the search argument and the keys result in a selection of one of four index values. These index values are used to address records in the next stage of the look-up. ...
Page 95
... This second stage of TCP port number look-up utilizes four records. Three TCP port number keys are stored in each record. The comparisons between the search argument and the keys result in a selection of one of four index values. These index values are used to address records in the next stage of the look-up. ...
Page 96
... Field Name tcp_key_{0..2}[15:0] This third stage of TCP port number look-up utilizes 16 records. Three TCP port number keys are stored in each record. The comparisons between the search argument and the keys result in a selection of one of four index val- ues. These index values are used to address records in the next stage of the look-up. ...
Page 97
... Field Name tcp_key_{0..2}[15:0] This fourth stage of TCP port number look-up utilizes 64 records. Three TCP port number keys are stored in each record. The comparisons between the search argument and the keys result in a selection of one of four index val- ues. These index values are used to address records in the next stage of the look-up. ...
Page 98
... This fifth and final stage of TCP port number look-up utilizes 256 records. Two TCP port number keys are stored in each record. The comparisons between the search argument and the keys result in a selection of one of three result values. These are returned as the final output of the look-up process. ...
Page 99
... Table 100. Acl_Vlan_Index_Table Field Parameters Field Name acl_index[5:0] The 8-bit VLAN index assigned to the receive packet is used as an address into this table. The addressed value is used as the ACL index for the packet. Essentially, this table provides a 256 to 64 mapping function. Agere Systems Inc. ...
Page 100
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Device_Version Description: This register returns version number for the device. Table 101. Device_Version Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing major_revision[11:0] Figure 73 ...
Page 101
... Table 104. Layer_2_Active_Port_Map Field Parameters Field Name active_port_map[57:0] This field is used to identify those ports that are enabled to forward Ethernet traffic in a normal manner. This infor- mation is used in determining whether or not a packet has been prevented from being forwarded due to VLAN mis- matches. ...
Page 102
... When the look- packet’s destination address indicates that its destination port is part of an aggregation of ports, then all of the ports in that aggregate are enabled by the initial destination map. The mask value retrieved from this table is used to select one of the ports from within the aggregate. ...
Page 103
... Table 108. Layer_2_Blocking_Mask Field Parameters Field Name blocking_mask[57:0] This mask is applied to the destination port map if the packet’s source port or VLAN is in the blocking state accord- ing to spanning tree rules. Bits asserted in blocking_mask[57:0] have the effect of disabling the corresponding destinations. PORT ...
Page 104
... Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 80. Layer_2_Current_Time Register Diagram Table 110. Layer_2_Current_Time Field Parameters Field Name current_time[3:0] When a known source address is received, its timestamp is updated in Layer_2_Time_Stamp_Table. The value written to that table is Layer_2_Current_Time.current_time[3:0]. 104 Value 0x000c_4660 ...
Page 105
... This table is addressed by the layer_2_dest_map_index[8:0] value returned as part of the associated data from the destination MAC address look-up. The value retrieved from this table is a destination port map. Bits are asserted in these map values to indicate destinations for the packet. This initial port map is adjusted through sev- eral steps of masking (eliminating destinations) and mapping (adding destinations) ...
Page 106
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Layer_2_Dest_Mirror_Map Description: A map of the destination ports configured to be mirrored. Table 113. Layer_2_Dest_Mirror_Map Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 83. Layer_2_Dest_Mirror_Map Register Diagram Table 114 ...
Page 107
... Figure 85. Layer_2_Flood_Map Register Diagram Table 116. Layer_2_Flood_Map Field Parameters Field Name flood_map[57:0] When a receive packet’s destination address is not found in the Layer 2 address table, this flood map is used as the initial destination map. PORT SU7 SU6 SU1 REFERENCE Agere Systems Inc. Value ...
Page 108
... Record Spacing Figure 87. Layer_2_Global_Mask Register Diagram Table 118. Layer_2_Global_Mask Field Parameters Field Name global_mask[57:0] Setting a bit in this register disables packets from being forwarded to the corresponding port. Supervisor transmis- sions are not affected by Layer_2_Global_Mask. PORT SU7 SU6 REFERENCE 57 56 108 Value 0x000c_4640 ...
Page 109
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Layer_2_Igmp_Snooping_Port Description: Identifies the port to be used for IGMP snooping. Table 119. Layer_2_Igmp_Snooping_Port Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances ...
Page 110
... Field Name layer_2_key_{0..2}[47:0] This first stage of a MAC address look-up involves the use of a single record containing three keys. The three keys are compared against the search argument. The results of these comparisons serve to select one of the four index values for use in the next stage of the look-up. ...
Page 111
... Field Name layer_2_key_{}{0..2}[47:0] This second stage of a MAC address look-up involves the use of four records, each containing three keys. The three keys are compared against the search argument. The results of these comparisons serve to select one of the four index values for use in the next stage of the look-up. ...
Page 112
... Field Name layer_2_key_{0..2}[47:0] This third stage of a MAC address look-up involves the use of 16 records, each containing three keys. The three keys are compared against the search argument. The results of these comparisons serve to select one of the four index values for use in the next stage of the look-up. ...
Page 113
... Field Name layer_2_key_{0..2}[47:0] This fourth stage of a MAC address look-up involves the use of 64 records, each containing three keys. The three keys are compared against the search argument. The results of these comparisons serve to select one of the four index values for use in the next stage of the look-up. ...
Page 114
... Field Name layer_2_key_{0..2}[47:0] This fifth stage of a MAC address look-up involves the use of 256 records, each containing three keys. The three keys are compared against the search argument. The results of these comparisons serve to select one of the four index values for use in the next stage of the look-up. ...
Page 115
... Field Name layer_2_key_{0..2}[47:0] This sixth stage of a MAC address look-up involves the use of 1,024 records, each containing three keys. The three keys are compared against the search argument. The results of these comparisons serve to select one of the four index values for use in the next stage of the look-up. ...
Page 116
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Layer_2_Key_Table_6 Description: The seventh and final stage of a MAC address look-up is performed by this table. Table 133. Layer_2_Key_Table_6 Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances ...
Page 117
... This seventh and final stage of a MAC address look-up involves the use of 4,096 records, each containing two keys and two associated data values. The two keys are compared against the search argument. The results of these comparisons serve to select one of the two associated data values as the final output of the look-up. ...
Page 118
... Table 136. Layer_2_Learning_Mask Field Parameters Field Name learning_mask[57:0] This mask is applied to the destination port map if the packet’s source port or VLAN is in the learning state accord- ing to spanning tree rules. Bits asserted in learning_mask[57:0] have the effect of disabling the corresponding destinations. PORT ...
Page 119
... Table 138. Layer_2_Learning_Port Field Parameters Field Name learning_port[5:0] When a packet is received whose MAC source address is not found in the address table or whose source port listed in the address table does not match the logical port through which it was received copied to the port number specified here. PORT SU7 ...
Page 120
... Field Name logical_port_{0..51}[5:0] The physical receive port number of a packet is used as an index into this table to determine the packet’s logical receive port. Logical port numbers are used to allow multiple physical ports to share a single identity. This capability reduces learning thrashing when packets are received on ports that are members of an aggregate. ...
Page 121
... Figure 104. Layer_2_Mirror_Port Register Diagram Table 142. Layer_2_Mirror_Port Field Parameters Field Name mirror_port[5:0] When mirroring is enabled and a packet is received or transmitted via a port that is being mirrored, that packet is also copied to the port identified by this register. PORT SU7 SU6 REFERENCE 57 56 Agere Systems Inc. ...
Page 122
... Mode = R/W Offset = 0.30, Instances = 1 Reset = 0 igmp_snoop_en Mode = R/W Offset = 0.31 Instances = 1 Reset = 0 This register contains an assortment of Layer 2 processing mode bits and fields. There is one record for each phys- ical Ethernet port. PORT XG1 XG0 SU1 SU0 G47 REFERENCE 60 50 ...
Page 123
... Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 108. Layer_2_No_Dest_Packets Register Diagram Table 146. Layer_2_No_Dest_Packets Field Parameters Field Name no_dest_packets[27: packet’s destination map is null (i.e., no destinations), then this counter is incremented. Agere Systems Inc. Value 0x000c_4680 ...
Page 124
... Field Name src_deny_mask[57:0] If the MAC source address look-up returns a source deny indication, then the ports identified by this mask are elim- inated as destinations for the packet. Asserted bits in src_deny_mask[57:0] identify those ports that are elimi- nated (masked) by this function. Deasserted bits in src_deny_mask[57:0] have no effect on the packet’s destination port map ...
Page 125
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Layer_2_Src_Mirror_Map Description: Identifies those ports whose receive traffic mirrored. Table 149. Layer_2_Src_Mirror_Map Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances ...
Page 126
... Table 152. Layer_2_Src_Port_Mask_Table Field Parameters Field Name src_port_mask[57:0] Mode = R/W Offset = 0.6 Instances = 1 Reset = 0 Source port masking is used to limit the destination ports reachable from each source port. There is a mask in the table for each of the system’s source ports. PORT SU7 SU6 REFERENCE 57 ...
Page 127
... Table 154. Layer_2_Supervisor_Route_Port Field Parameters Field Name supervisor_route_port[5:0] When a receive packet’s MAC source address is found in the address table but the source VLAN and destination VLAN do not match and supervisor routing is enabled, this port is added to the packet’s destination port map. PORT ...
Page 128
... Field Name time_stamp[3:0] This table holds the time stamps for the MAC address table. Whenever an address in the MAC address table is seen in a received packet as a source address and the received packet’s source port matches the source port information in the address table, the time stamp value in this table that corresponds to that MAC address table entry is updated with the current time value ...
Page 129
... Figure 118. Layer_2_User_Port Register Diagram Table 158. Layer_2_User_Port Field Parameters Field Name user_port[15:0] A single TCP destination port may be specified for snooping purposes enabled, any packet with a TCP desti- nation port value that matches the value here is copied to the port specified by Layer_2_User_Port_Snooping_Port. Agere Systems Inc. ...
Page 130
... Figure 119. Layer_2_User_Port_Snooping_Port Register Diagram Table 160. Layer_2_User_Port_Snooping_Port Field Parameters Field Name user_port_snooping_port[5:0] If the TCP destination port number of the received packet matches the value in Layer_2_User_Port and Layer_2_Mode.user_port_snoop_en is asserted, then the port specified by the value in user_port_snooping_port[5:0] is added to the packet’s destination port map. PORT ...
Page 131
... Figure 121. Layer_2_Vlan_Mask_Table Register Diagram Table 162. Layer_2_Vlan_Mask_Table Field Parameters Field Name vlan_mask[57:0] The received packet’s 8-bit VLAN index is used to retrieve a port mask from this table. This mask is then used to eliminate destinations from the packet’s destination port map. PORT SU7 ...
Page 132
... Field Name stp_state[1:0] In order to support per VLAN spanning tree, the spanning tree state of each port must be maintained on a per- VLAN basis. This table provides this information to the bridging function. This table is addressed by a concatenation of the packet’s receive port and the packet’s VLAN index: ...
Page 133
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Mac_Global_Mode Description: Sets basic shared operating modes for the Ethernet MACs. Table 165. Mac_Global_Mode Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size ...
Page 134
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Appendix A: Registers (continued) Mac_Global_Mode (continued) Table 166. Mac_Global_Mode Field Parameters (continued) Field Name inject_offset_polarity loopback_delay_select[1:0] loopback_amplitude_select inject_offset_2 inject_offset_1 inject_offset_0 sw_reset_control rprog[5:0] set_resistor_value_{0..2}[2:0] force_resistor_{0..2} resistor_compensation_status_{0..2}[2:0] 134 Parameters Mode = R/W This bit establishes the polarity of the offset specified Offset = 8 ...
Page 135
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Mac_Mode_{0..4} Description: Sets basic operating modes for the Ethernet MACs. Table 167. Mac_Mode_{0..4} Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances ...
Page 136
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Appendix A: Registers (continued) Mac_Mode_{0..4} (continued) Table 168. Mac_Mode_{0..4} Field Parameters (continued) Field Name input_select_{}{0..9}[1:0] speed_mode_force_{}{0..9}[1:0] good_link_force_{}{0..9} full_duplex_force_{}{0..9} auto_negotiate_en_{}{0..9} restart_auto_negotiation_{}{0..9} gmac_tx_flush_{}{0..9} gmac_port_speed_{}{0..9}[1:0] gmac_port_loopback_en_{}{0..9} 136 ...
Page 137
... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Mac_Mode_{0..4} (continued) Table 168. Mac_Mode_{0..4} Field Parameters (continued) Field Name gmac_rx_en_{}{0..9} gmac_flow_control_initiate_en_{}{0..9} gmac_rx_pause_en_{}{0..9} PORT XG1 XG0 SU1 SU0 G47 REFERENCE Agere Systems Inc. Parameters Mode = R/W Enables the reception of Ethernet packets ...
Page 138
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Mac_Mode_{5..6} Description: Sets basic operating modes for the Ethernet MACs. Table 169. Mac_Mode_{5..6} Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 128. Mac_Mode_{5..6} Register Diagram Table 170 ...
Page 139
... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Mac_Mode_{5..6} (continued) Table 170. Mac_Mode_{5..6} Field Parameters (continued) Field Name less_aggress_mode xgmac_rx_en xgmac_flow_control_initiate_en xgmac_rx_pause_en PORT XG1 REFERENCE 60 Agere Systems Inc. Parameters Mode = R/W When asserted, the minimum interframe gap for the Offset = 0 ...
Page 140
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Mac_Status_{0..4} Description: Indicates fundamental status for the Ethernet MACs. Table 171. Mac_Status_{0..4} Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 130. Mac_Status_{0..4} Register Diagram Table 172 ...
Page 141
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Mdio_Control Description: Provides supervisor control of the MDIO interfaces. Table 173. Mdio_Control Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing ...
Page 142
... For writes, the write data is simply written to offset 0 of this register with an opcode of 01 causes mdio_busy to be asserted by the MDIO interface controller. This signal is deasserted automatically upon completion of the MDIO access cycle ...
Page 143
... Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Mdio_Control (continued) There are three MDIO interfaces on the ET4148-50 device. The following table defines how the interfaces are selected and how the interfaces are used in a system. Table 175. MDIO Interface Selection MDIO mdio_interface_select 0 ...
Page 144
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Mdio_Mode Description: Defines the basic mode for the MDIO interfaces. Table 176. Mdio_Mode Register Parameters Parameter Base Address 0x000c_8308 Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing ...
Page 145
... Mdio_Mode (continued) This register is used to define the characteristics of the MDIO clock. The period of the MDIO clock is established by mdio_clk_period[7:0]. The value of this field establishes a terminal count which, in turn, defines the half- clock period for the MDIO clock. A free-running counter counts up until reaching mdio_clk_period[7:0]. When this value is reached, the free-running counter is reset to zero and the MDIO clock signal is toggled ...
Page 146
... This register provides basic status regarding MDIO access cycles. mdio_busy provides the same information as the signal of the same name in Mdio_Control. mdio_done is automatically asserted upon completion of an MDIO access cycle. This signal is also used as an interrupt-generating indication to the supervisor. The supervisor must write a zero to this bit’s position to deassert the bit and cancel the indication ...
Page 147
... Table 181. Multicast_Rate_Accumulator Field Parameters Field Name multicast_rate_accumulator[15:0] This leaky bucket counter is incremented by the reception of multicast and broadcast packets and is decremented by one on a fixed interval. That interval is defined by the contents of the Multicast_Rate_Decrement_Period register. Whenever the value of multicast_rate_accumulator[15:0] exceeds Multicast_Rate_Limit, the mask in Multicast_Rate_Discard_Mask is applied to the receive packet’s destination map ...
Page 148
... This register specifies the number periods between decrements of Multicast_Rate_Accumulator. The minimum value of one results in a decrement once every 8 ns total multicast/broadcast packet rate of 125,000,000 per second. This register’s maximum value of 1,048,575 results in a total multicast/broadcast packet rate of 119 per second. ...
Page 149
... Figure 137. Multicast_Rate_Discard_Mask Register Diagram Table 185. Multicast_Rate_Discard_Mask Field Parameters Field Name multicast_rate_discard_mask[57:0] This mask is applied to the destination port map if the value of Multicast_Rate_Accumulator is greater than Multicast_Rate_Limit. This mask is only applied to multicast and broadcast packets. PORT SU7 SU6 REFERENCE 57 56 Agere Systems Inc. ...
Page 150
... The maximum value allowed in Multcast_Rate_Limit is FFFE The actual multicast rate is established via the Multicast_Rate_Decrement_Period register. Multicast_Rate_Limit merely establishes this function’s tolerance of bursts of multicast and broadcast packets. A larger value of multicast_rate_limit[15:0] allows longer bursts of multicast and broadcast packet before the discarding of these packets kicks in. 150 ...
Page 151
... Multicast_Rate_Accumulator is greater than Multicast_Rate_Limit and Multicast_Rate_Limit is greater than zero. Note: The application of the multicast rate discard mask may not result in the reduction of the number of destina- tions for a multicast packet. For example, BPDU packets ordinarily should not be discarded by this function and Multicast_Rate_Discard_Mask is normally configured to avoid masking the supervisor’s BPDU queue ...
Page 152
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Multicast_Rate_Mode Description: Mode bits for the multicast rate limiting function. Table 190. Multicast_Rate_Mode Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 141. Multicast_Rate_Mode Register Diagram Table 191 ...
Page 153
... Field Name acl_deny_mask[57:0] If the ACL look-up returns a deny indication, then the ports identified by this mask are eliminated as destinations for the packet. Asserted bits in acl_deny_mask[57:0] identify those ports that are eliminated (masked) by this function. Deasserted bits in acl_deny_mask[57:0] have no effect on the packet’s destination port map. ...
Page 154
... Table 195. Packet_Buffer_Acl_Log_Port Field Parameters Field Name acl_log_port[5:0] If the ACL look-up returns a log indication, then the port identified by this value is added to the packet’s destination port map. Most typically, one of the supervisor’s queues (ports 50 through 57) are designated as the ACL logging port. ...
Page 155
... Record Instances Record Spacing Figure 146. Packet_Buffer_Allocated_Buffer_Count Register Diagram Table 197. Packet_Buffer_Allocated_Buffer_Count Field Parameters Field Name allocated_buffer_count[13:0] This register provides a real-time indication of the number of buffers that are allocated per port. PORT XG1 XG0 SU1 SU0 G47 REFERENCE Agere Systems Inc. Value 0x000c_b900 ...
Page 156
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Channel_Congestion_Threshold Description: Per-channel congestion thresholds. Table 198. Packet_Buffer_Channel_Congestion_Threshold Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing mac_channel_congestion_threshold[14:4] Figure 148. Packet_Buffer_Channel_Congestion_Threshold Register Diagram Table 199 ...
Page 157
... Field Name crc_error_mask[57:0] If the packet is received with a CRC error (or some other form of receive error that indicates corrupted or unreliable packet data), then the ports identified by this mask are eliminated as destinations for the packet. Asserted bits in crc_error_mask[57:0] identify those ports that are eliminated (masked) by this function. Deasserted bits in crc_error_mask[57:0] have no effect on the packet’ ...
Page 158
... Table 203. Packet_Buffer_Descriptor_Congestion_Threshold Field Parameters Field Name mac_descriptor_congestion_threshold[13:4] policer_descriptor_congestion_threshold[13:4] Packet descriptors are managed in four groups. The global thresholds defined by this register apply to all four groups. If any one of the four groups exceed an allocation threshold, then the threshold is considered crossed by all four groups. 158 Value 0x000c_bc5c ...
Page 159
... Figure 152. Packet_Buffer_Descriptor_Usage_Count Register Diagram Table 205. Packet_Buffer_Descriptor_Usage_Count Field Parameters Field Name descriptor_usage_count[13:0] This register provides a real-time indication of the number of descriptors that have been allocated to one of four port groups. Ports are grouped together as follows: Table 206. Port/Group Associations Group 12, 16, 20, 24, 28, 32, 36, 40, 44, 50 ...
Page 160
... Field Name discard_mask[57:0] If the packet is marked for discard by some ingress process, then the ports identified by this mask are eliminated as destinations for the packet. Asserted bits in discard_mask[57:0] identify those ports that are eliminated (masked) by this function. Deasserted bits in discard_mask[57:0] have no effect on the packet’s destination port map ...
Page 161
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Packet_Buffer_Free_Buffer_Control Description: Free buffer list initialization controls. Table 209. Packet_Buffer_Free_Buffer_Control Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing ...
Page 162
... Figure 156. Packet_Buffer_Free_Buffer_Count_Even Register Diagram Table 212. Packet_Buffer_Free_Buffer_Count_Even Field Parameters Field Name free_buffer_count_even[12:0] This register provides a real-time indication of the number of buffers that reside on the free list. Smaller numbers read here indicate greater levels of congestion. This register corresponds to all even-numbered buffers. 162 ...
Page 163
... Figure 157. Packet_Buffer_Free_Buffer_Count_Odd Register Diagram Table 214. Packet_Buffer_Free_Buffer_Count_Odd Field Parameters Field Name free_buffer_count_odd[12:0] This register provides a real-time indication of the number of buffers that reside on the free list. Smaller numbers read here indicate greater levels of congestion. This register corresponds to all odd-numbered buffers. Agere Systems Inc. ...
Page 164
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Free_Descriptor_Control Description: Free buffer list initialization controls. Table 215. Packet_Buffer_Free_Descriptor_Control Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 158. Packet_Buffer_Free_Descriptor_Control Register Diagram Table 216 ...
Page 165
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Packet_Buffer_Global_Congestion_Threshold Description: Global congestion thresholds. Table 217. Packet_Buffer_Global_Congestion_Threshol Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing mac_global_congestion_threshold[14:4] Figure 159. Packet_Buffer_Global_Congestion_Threshold Register Diagram Table 218 ...
Page 166
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Ind Description: Provides supervisor indications from packet_buffer. Table 219. Packet_Buffer_Ind Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 160. Packet_Buffer_Ind Register Diagram Table 220 ...
Page 167
... Preliminary Data Sheet April 2006 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Ind (continued) Table 220. Packet_Buffer_Ind Field Parameters (continued) Field Name free_buffer_list_empty free_descriptor_list_empty queue_full rate_adaptation_fifo_overflow packet_buffer_ind_mask[6:0] packet_buffer_ind_mask_set[6:0] packet_buffer_ind_mask_clear[6:0] packet_buffer_int[6:0] packet_buffer_int_mask[6:0] packet_buffer_int_mask_set[6:0] packet_buffer_int_mask_clear[6:0] Various indications to the supervisor regarding packet_buffer. These indications may be masked by Packet_Buffer_Ind_Mask ...
Page 168
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Mode Description: Mode bits. Table 221. Packet_Buffer_Mode Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 161. Packet_Buffer_Mode Register Diagram Table 222. Packet_Buffer_Mode Field Parameters ...
Page 169
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Packet_Buffer_Packet_Drop_Count Description: Provides an accounting of various packet drop counts. Table 223. Packet_Buffer_Packet_Drop_Count Register Parameters Parameter Base Address Register Size (revision B and B1) Register Size (revision C) Register Instances Register Spacing ...
Page 170
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Packet_Drop_Count Table 224. Packet_Buffer_Drop_Count Field Parameters Field Name rxpc_correlator_discard_drop_count[31:0] destination_port_map_zero_drop_count[31:0] replication_fifo_full_drop_count[31:0] pdp_parity_error_drop_count[31:0] rxpc_runt_packet_drop_count_0[31:0] rxpc_runt_packet_drop_count_1[31:0] rxpc_runt_packet_drop_count_2[31:0] rxpc_runt_packet_drop_count_3[31:0] rxpc_runt_packet_drop_count_4[31:0] rxpc_runt_packet_drop_count_5[31:0] rxpc_runt_packet_drop_count_6[31:0] rxpc_txpc_discard_drop_count[31:0] replication_partial_drop_count[31:0] port_map_changed_drop_count[31:0] Various basic mode bits related to packet_buffer. 170 (continued) Parameters ...
Page 171
... Further parity errors do not cause changes to the value held by this register. In order to reprime this register for the capture of a subsequent error, all packet_buffer-related parity error indication bits in Packet_Buffer_Ind must first be reset ...
Page 172
... Table 228. Packet_Buffer_Port_Speed Field Parameters Field Name port_speed_{0..47}[1:0] This register provides per-port interface speed information to the traffic shapers. This register does not actually affect the speed of the Ethernet ports; it merely informs the packet buffer of the speed at which each port is operat- ing. PORT SU7 ...
Page 173
... Field Name storage_priority_{0..15}[2:0] The 16 levels of priority utilized during ingress packet processing are used to select one of eight transmit queues associated with each transmit port. This table is used to map between various priority levels and queues. This table is addressed by the packet’s priority level and returns the 3-bit queue selection value: storage_priority[2:0] ...
Page 174
... This register defines the number of buffers (128 bytes) that each queue is allowed to use during times of packet buffer congestion. If the buffer memory is congested and the number of buffers used for any supervisor queue exceeds supervisor_queue_buffer_limit[14:0] or the number of queued buffers for any other queue exceeds queue_buffer_limit[14:0], then that queue is disabled from receiving further entries queue is in excess of this limit when the packet buffer becomes congested, its excess queue entries are not discarded ...
Page 175
... Figure 168. Packet_Buffer_Queue_Buffers_{0..3} Register Diagram Table 234. Packet_Buffer_Queue_Buffers_{0..3} Field Parameters Field Name queue_buffers[14:0] This register provides the supervisor with the number of buffers that are currently associated with each of the queues. The queues are grouped according to the following table. Agere Systems Inc. Value ...
Page 176
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Queue_Buffers_{0..3} (Revision C Only) Table 235. Queue Groups Group 0 0—7 Queues 32—39 64—71 96—103 128—135 160—167 192—199 224—231 256—263 288—295 320—327 352—359 384—391 ...
Page 177
... Figure 170. Packet_Buffer_Queue_Depth_{0..3} Register Diagram Table 237. Packet_Buffer_Queue_Depth_{0..3} Field Parameters Field Name queue_depth[12:0] This register provides the supervisor with the number of buffers that are currently associated with each of the queues. The queues are grouped according to the following table. Agere Systems Inc. Value ...
Page 178
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Queue_Depth_{0..3} (Revision C Only) Table 238. Queue Groups Group 0 0—7 Queues 32—39 64—71 96—103 128—135 160—167 192—199 224—231 256—263 288—295 320—327 352—359 384—391 ...
Page 179
... This register defines the number of queue entries in packets that each queue is allowed to have during times of queue memory congestion. If the queue memory is congested and the number of queue entries for any supervisor queue exceeds the supervisor_queue_limit[12:0] or for any other queue exceeds the queue_limit[12:0] value, then that queue is disabled from receiving further entries queue is in excess of its limit when the queue memory becomes congested, its excess queue entries are not discarded ...
Page 180
... Record Instances Record Spacing queue_mask_congestion_threshold[14:4] Figure 173. Packet_Buffer_Queue_Management_Thresholds Register Diagram Table 242. Packet_Buffer_Management_Thresholds Field Parameters Field Name queue_mask_congestion_ threshold[14:4] buffer_queue_global_congestion_ threshold[14:4] This register is valid in revision C only, and the hol_mode bit in the packet_buffer_mode register must be asserted to use this register. 180 Value 0x000C_E208 ...
Page 181
... When one of queues is not empty, its cor- responding bit is asserted. When the queue is empty, its corresponding status bit is deasserted. Note: For revision C, the 10 Gbits/s Ethernet queues are spread across two entries in this table. XG0 is at refer- ences 50 and 52, while XG1 appears at references 51 and 53. ...
Page 182
... The number of packets dequeued in each bursts is defined by its corresponding queue_weight[3:0] value. For example, if the queue_weight[3:0] values for a set of four queues is 11 and 6, then 11 packets are dequeued from the first queue before one is dequeued from the next; three from the next after that, and then six from the last queue ...
Page 183
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Packet_Buffer_Scrub Description: Initiates and directs the scrubbing of lost buffers. Table 247. Packet_Buffer_Scrub Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances ...
Page 184
... Field Name shaper_accumulator_sign shaper_accumulator[15:4] The shaper accumulators are used to determine when a particular queue may have one of its packet’s scheduled for retrieval and transmission. A queue is considered eligible for scheduling when its corresponding shaper_accumulator[15:4] value is greater than zero. There is one shaper_accumulator[15:4] value per queue. ...
Page 185
... Field Name shaper_accumulator_sign shaper_accumulator[15:4] The shaper accumulators are used to determine when a particular queue may have one of its packet’s scheduled for retrieval and transmission. A queue is considered eligible for scheduling when its corresponding shaper_accumulator[15:4] value is greater than zero. There is one shaper_accumulator[15:4] value per queue. ...
Page 186
... Packet_Buffer_Shaper_Accumulator register field. The period of these applications of credit is derived from the system clock and is dependent on the bit rate of the associated interface period assumed for a 10 Gbits/s Ethernet port, then 10p is used for 1 Gbit/s, 100p for 100 Mbits/s, and 1000p for 10 Mbits/s. The nominal value for p is 1.28 µ ...
Page 187
... Packet_Buffer_Shaper_Accumulator register field. The period of these applications of credit is derived from the system clock and is dependent on the bit rate of the associated interface period assumed for a 10 Gbits/s Ethernet port, then 10p is used for 1 Gbit/s, 100p for 100 Mbits/s, and 1000p for 10 Mbits/s. The nominal value for p is 1.28 µ ...
Page 188
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Packet_Buffer_Shaper_Limit Description: An upper limit for shaper accumulators. Table 257. Packet_Buffer_Shaper_Limit Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 187. Packet_Buffer_Shaper_Limit Register Diagram Table 258 ...
Page 189
... Table 260. Policer_Accumulator_Table_{0..4} Field Parameters Field Name port_speed[1:0] policer_accumulator[17:0] Rx_Packet_Header.packet_length[13:0] is added to the policer_accumulator[17:0] field that cor- responds to the packet’s policer for each received packet. On regular intervals, policer_delta[7:0] is sub- tracted from policer_accumulator[17:0]. If policer_accumulator[17:0] exceeds policer_limit[17:11], then the traffic is considered out of profile. PORT XG1 ...
Page 190
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Policer_Accumulator_Table_{5..6} Description: This table is used to accumulate packet data rates. Table 261. Policer_Accumulator_Table_{5..6} Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 190. Policer_Accumulator_Table_{5..6} Register Diagram Table 262 ...
Page 191
... Ethernet receive port. The nominal service interval for a 1 Gbit/s port is once every 12.8 µs or 78,125 times per second. In addition, the service interval for a 100 Mbits/s port is 1/10 that Gbit/s port; and for a 10 Mbits/s port, 1/100 that Gbit/s port. ...
Page 192
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Policer_Delta_Table_{0..4} (continued) . PORT XG1 REFERENCE 60 192 PORT NUMBERING SCHEME XG0 SU1 SU0 G47 G46 G45 G44 10/100/1000 Mbits/s PORT Gbits/s PORT SU = SUPERVISOR Figure 193. Port Numbering Scheme Agere Systems - Proprietary Preliminary Data Sheet ...
Page 193
... Larger policer_delta[6:0] values translate into higher allowed data rates on the corresponding policer. When subtracted from the Policer_Accumulator_Table, a product of 16 (policer_delta[6:0] = 0x1) results in a service interval of 12.5 Mbytes/s or 100 Mbits/s. This Gbits/s. A product of 1,600 (policer_delta[6:0] = 0x64) results in a service interval of 1,250 Mbytes Gbits/s. This is, of course, 100% of the interface’ ...
Page 194
... The dest_flow_id[2:0] and src_flow_id[2:0] values are derived from either the packet’s Layer 2 address look-up or its Layer 3 address look-up. The Layer 3 values are used if the packet contains a valid IPv4 or IPv6 header and Policer_Mode.layer_2_flow_id_override_en is not asserted. Otherwise, the packet’s Layer 2 destination and source address values are used. ...
Page 195
... The dest_flow_id[2:0] and src_flow_id[2:0] values are derived from either the packet’s Layer 2 address look-up or its Layer 3 address look-up. The Layer 3 values are used if the packet contains a valid IPv4 or IPv6 header and Policer_Mode.layer_2_flow_id_override_en is not asserted. Otherwise, the packet’s Layer 2 destination and source address values are used. ...
Page 196
... This register provides an assortment of flow-specific mode settings. For the channelized packet_processor modules (numbers 0 through 4), the eighty policer mode sets are allocated eight per channel. Policers 0 through 7 are allocated to channel 0, policers 8 through 15 to channel 1, etc. For the nonchannelized packet_processor modules (numbers 5 and 6), all eighty policer mode sets are allo- cated to the eighty policers of the single channel ...
Page 197
... This register provides an assortment of flow-specific mode settings. For the channelized packet_processor modules (numbers 0 through 4), the eighty policer mode sets are allocated eight per channel. Policers 0 through 7 are allocated to channel 0, policers 8 through 15 to channel 1, etc. For the nonchannelized packet_processor modules (numbers 5 and 6), all eighty policer mode sets are allo- cated to the eighty policers of the single channel ...
Page 198
... ET4148-50 Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch Appendix A: Registers (continued) Policer_Limit_Table_{0..4} Description: Establishes the bandwidth limit for each flow. Table 275. Policer_Limit_Table_{0..4} Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances Record Spacing Figure 204. Policer_Limit_Table_{0..4} Register Diagram Table 276 ...
Page 199
... Preliminary Data Sheet Single-Chip Gbit Gbits/s Layer 2+ Ethernet Switch April 2006 Appendix A: Registers (continued) Policer_Limit_Table_{5..6} Description: Establishes the bandwidth limit for each flow. Table 277. Policer_Limit_Table_{5..6} Register Parameters Parameter Base Address Register Size Register Instances Register Spacing Record Size Record Instances ...
Page 200
... A collection of per-policer aggregate mode bits. Each packet_processor module includes an aggregate policer function. Each aggregate consists of 80 policer functions (eight per port for the 1 Gbit/s Ethernet ports and 80 per port for the 10 Gbits/s Ethernet ports). The mode bits in this register act globally on a policer aggregate, not on individual policers. ...