L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 47

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Data Structures
Supervisor_Rx_Fifo_{0..7}
Description: An assortment of receive packets.
Table 8. Supervisor_Rx_Fifo_{0..7} Register Parameters
This data structure is a collection of Supervisor_Rx_Packet data structures.
The physical extent of Supervisor_Rx_Fifo{0..7} is defined by Supervisor_Rx_Fifo_Limits_{0..7}.
Base Address
Structure Size
Structure Instances
Structure Spacing
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
1
Parameter
2
3
4
5
6
Figure 22. Supervisor_Rx_Fifo_{0..7} Data Structure
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
8
9
10
Supervisor_Rx_Fifo_Limits_{0..1}.start[31:2]
Supervisor_Rx_Fifo_Limits_{0..1}.end[31:2] –
Supervisor_Rx_Fifo_Limits_{0..1}.start[31:2] + 4
Agere Systems - Proprietary
11
12
Supervisor_Rx_Packet
Supervisor_Rx_Packet
13
14
15
16
17
18
19
20
Variable
21
Value
8
22
23
8
24
7
25
6
26
5
27
4
28
3
29
2
30
1
ET4148-50
31
0
47