L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 265

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Vlan_Port_Protocol_Table_{5..6}
Description: This table converts port numbers and protocol indexes into VLAN indexes.
Table 376. Vlan_Port_Protocol_Table_{5..6} Register Parameters
Table 377. Vlan_Port_Protocol_Table_{5..6} Field Parameters
A 3-bit ethertype index is used as an address into this table. The value returned is an entry_valid indication and
a VLAN index for use in all ingress and egress packet processing. If entry_valid is false, vlan_index[7:0] is
invalid.
Care must be taken when configuring this table to ensure consistency from one packet processor to the next (e.g.,
the accidental or inconsistent reuse of VLAN index values).
This table is addressed by protocol_index[2:0].
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
entry_valid_{}{0..7}
vlan_index_{}{0..7}[7:0]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Parameter
Field Name
1
2
3
REFERENCE
4
Figure 288. Vlan_Port_Protocol_Table_{5..6} Register Diagram
5
PORT
6
7
XG1
60
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
XG0
50
9
Figure 289. Port Numbering Scheme
10
SU1
49
Agere Systems - Proprietary
Instances = 1
Instances = 1
Offset = 0.20
Mode = R/W
Mode = R/W
Parameters
11
Offset = 0.0
0x0007_5c00
SU0
PORT NUMBERING SCHEME
48
12
32768
Value
G = 10/100/1000 Mbits/s PORT
XG = 10 Gbits/s PORT
SU = SUPERVISOR
13
G47
32
47
2
4
8
4
14
G46
46
15
16
G45
45
17
This bit is asserted to indicate that the associated
VLAN index value is valid.
The VLAN identifier as selected by the packet’s
protocol.
G44
44
18
19
20
21
22
G3
3
23
8
Description
24
7
G2
2
25
6
G1
1
vlan_index[7:0]
26
5
27
G0
4
0
28
3
29
2
30
1
ET4148-50
31
0
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