L-ET4148-50C-DB LSI, L-ET4148-50C-DB Datasheet - Page 247

• Manufacturer Part Number: L-ET4148-50C-DB
• Manufacturer: LSI

Specifications of L-ET4148-50C-DB

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Preliminary Data Sheet
April 2006
Agere Systems Inc.
Appendix A: Registers
Supervisor_Tx_Fifo_Ptr
Description: The pointers used in managing the supervisor’s transmit packet FIFOs.
Table 346. Supervisor_Tx_Fifo_Ptr Register Parameters
Table 347. Supervisor_Tx_Fifo_Ptr Field Parameters
These pointers are used during the operation of the transmit FIFOs. There are two instances of the single-field
record diagrammed above. The record at offset zero corresponds to transmit FIFO zero.
As the ET4148-50 processes the packet transmit FIFO, it advances tx_fifo_rd_ptr[31:2]. The supervisor
reads this register to determine if its next FIFO entry might overwrite the end of the FIFO. If the address of the
supervisor’s next FIFO write location is equal to tx_fifo_rd_ptr[31:2], then that FIFO is full. When
tx_fifo_rd_ptr[31:2] and Supervisor_Tx_Fifo_Limits.tx_fifo_last_ptr[31:2] are equal, then
the corresponding FIFO is empty.
Base Address
Register Size
Register Instances
Register Spacing
Record Size
Record Instances
Record Spacing
tx_fifo_rd_ptr[31:2]
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0
Field Name
1
Parameter
2
3
4
5
6
Figure 259. Supervisor_Tx_Fifo_Ptr Register Diagram
7
Single-Chip 48 x 1 Gbit/s + 2 x 10 Gbits/s Layer 2+ Ethernet Switch
(continued)
8
9
10
Agere Systems - Proprietary
Instances = 1
0x000c_c440
Mode = R/W
Parameters
Offset = 4.0
11
Value
12
NA
tx_fifo_rd_ptr[31:2]
8
1
4
2
4
13
14
15
16
17
Defines the location within supervisor memory of
the transmit FIFO entry currently being processed
by the ET4148-50. This pointer is maintained by the
ET4148-50 and interpreted by the supervisor.
18
19
20
21
22
23
8
Description
24
7
25
6
26
5
27
4
28
3
29
2
30
1
0
ET4148-50
31
0
0
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